[1/2] mtd: spi-nore: core: Add in framework for 8S-8S-8S Octal STR mode
Commit Message
While trying to bring up an Octal SPI device in STR mode, I found
that there is currently no support for 8S-8S-8S. This patch adds
the necessary, additional logic for doing so.
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
---
drivers/mtd/spi-nor/core.c | 57 ++++++++++++++++++++++++++++++++++++--
drivers/mtd/spi-nor/core.h | 5 +++-
2 files changed, 59 insertions(+), 3 deletions(-)
Comments
Hi Nathan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v6.1-rc6]
[also build test ERROR on linus/master next-20221125]
[cannot apply to mtd/spi-nor/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Nathan-Barrett-Morrison/These-are-the-required-patches-I-found-while-adding/20221124-051608
patch link: https://lore.kernel.org/r/20221123211335.126417-2-nathan.morrison%40timesys.com
patch subject: [PATCH 1/2] mtd: spi-nore: core: Add in framework for 8S-8S-8S Octal STR mode
config: x86_64-randconfig-a001
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/47217ef33736ae6ec01261ed674a9516aa0d6709
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Nathan-Barrett-Morrison/These-are-the-required-patches-I-found-while-adding/20221124-051608
git checkout 47217ef33736ae6ec01261ed674a9516aa0d6709
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/mtd/spi-nor/core.c:2365:30: warning: array index 8192 is past the end of the array (which contains 16 elements) [-Warray-bounds]
spi_nor_set_read_settings(¶ms->reads[SNOR_HWCAPS_READ_8_8_8],
^ ~~~~~~~~~~~~~~~~~~~~~~
drivers/mtd/spi-nor/core.h:387:2: note: array 'reads' declared here
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
^
>> drivers/mtd/spi-nor/core.c:2658:20: error: no member named 'octal_str_enable' in 'struct spi_nor_flash_parameter'; did you mean 'octal_dtr_enable'?
if (!nor->params->octal_str_enable)
^~~~~~~~~~~~~~~~
octal_dtr_enable
drivers/mtd/spi-nor/core.h:393:8: note: 'octal_dtr_enable' declared here
int (*octal_dtr_enable)(struct spi_nor *nor, bool enable);
^
drivers/mtd/spi-nor/core.c:2668:21: error: no member named 'octal_str_enable' in 'struct spi_nor_flash_parameter'; did you mean 'octal_dtr_enable'?
ret = nor->params->octal_str_enable(nor, enable);
^~~~~~~~~~~~~~~~
octal_dtr_enable
drivers/mtd/spi-nor/core.h:393:8: note: 'octal_dtr_enable' declared here
int (*octal_dtr_enable)(struct spi_nor *nor, bool enable);
^
1 warning and 2 errors generated.
vim +2658 drivers/mtd/spi-nor/core.c
2647
2648 /** spi_nor_octal_str_enable() - enable Octal STR I/O if needed
2649 * @nor: pointer to a 'struct spi_nor'
2650 * @enable: whether to enable or disable Octal STR
2651 *
2652 * Return: 0 on success, -errno otherwise.
2653 */
2654 static int spi_nor_octal_str_enable(struct spi_nor *nor, bool enable)
2655 {
2656 int ret;
2657
> 2658 if (!nor->params->octal_str_enable)
2659 return 0;
2660
2661 if (!(nor->read_proto == SNOR_PROTO_8_8_8 &&
2662 nor->write_proto == SNOR_PROTO_8_8_8))
2663 return 0;
2664
2665 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
2666 return 0;
2667
2668 ret = nor->params->octal_str_enable(nor, enable);
2669 if (ret)
2670 return ret;
2671
2672 if (enable)
2673 nor->reg_proto = SNOR_PROTO_8_8_8;
2674 else
2675 nor->reg_proto = SNOR_PROTO_1_1_1;
2676
2677 return 0;
2678 }
2679
@@ -2253,7 +2253,8 @@ static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
{
if (nor->params->addr_nbytes) {
nor->addr_nbytes = nor->params->addr_nbytes;
- } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
+ } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR ||
+ nor->read_proto == SNOR_PROTO_8_8_8) {
/*
* In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
* in this protocol an odd addr_nbytes cannot be used because
@@ -2335,7 +2336,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
struct spi_nor_erase_map *map = ¶ms->erase_map;
- const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
+ const u16 no_sfdp_flags = nor->info->no_sfdp_flags;
u8 i, erase_mask;
if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
@@ -2359,6 +2360,13 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
SNOR_PROTO_1_1_8);
}
+ if (no_sfdp_flags & SPI_NOR_OCTAL_STR_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_HWCAPS_READ_8_8_8],
+ 0, 20, SPINOR_OP_READ_FAST,
+ SNOR_PROTO_8_8_8);
+ }
+
if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
@@ -2366,6 +2374,12 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
SNOR_PROTO_8_8_8_DTR);
}
+ if (no_sfdp_flags & SPI_NOR_OCTAL_STR_PP) {
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8;
+ spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8],
+ SPINOR_OP_PP, SNOR_PROTO_8_8_8);
+ }
+
if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {
params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
/*
@@ -2631,6 +2645,38 @@ static int spi_nor_init_params(struct spi_nor *nor)
return 0;
}
+/** spi_nor_octal_str_enable() - enable Octal STR I/O if needed
+ * @nor: pointer to a 'struct spi_nor'
+ * @enable: whether to enable or disable Octal STR
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_octal_str_enable(struct spi_nor *nor, bool enable)
+{
+ int ret;
+
+ if (!nor->params->octal_str_enable)
+ return 0;
+
+ if (!(nor->read_proto == SNOR_PROTO_8_8_8 &&
+ nor->write_proto == SNOR_PROTO_8_8_8))
+ return 0;
+
+ if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
+ return 0;
+
+ ret = nor->params->octal_str_enable(nor, enable);
+ if (ret)
+ return ret;
+
+ if (enable)
+ nor->reg_proto = SNOR_PROTO_8_8_8;
+ else
+ nor->reg_proto = SNOR_PROTO_1_1_1;
+
+ return 0;
+}
+
/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
* @nor: pointer to a 'struct spi_nor'
* @enable: whether to enable or disable Octal DTR
@@ -2691,6 +2737,12 @@ static int spi_nor_init(struct spi_nor *nor)
return err;
}
+ err = spi_nor_octal_str_enable(nor, true);
+ if (err) {
+ dev_dbg(nor->dev, "octal STR mode not supported\n");
+ return err;
+ }
+
err = spi_nor_quad_enable(nor);
if (err) {
dev_dbg(nor->dev, "quad mode not supported\n");
@@ -2714,6 +2766,7 @@ static int spi_nor_init(struct spi_nor *nor)
if (nor->addr_nbytes == 4 &&
nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
+ nor->read_proto != SNOR_PROTO_8_8_8 &&
!(nor->flags & SNOR_F_4B_OPCODES)) {
/*
* If the RESET# pin isn't hooked up properly, or the system
@@ -359,6 +359,7 @@ struct spi_nor_otp {
* Table.
* @otp: SPI NOR OTP info.
* @octal_dtr_enable: enables SPI NOR octal DTR mode.
+ * @octal_str_enable: enables SPI NOR octal STR mode.
* @quad_enable: enables SPI NOR quad mode.
* @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
* @convert_addr: converts an absolute address into something the flash
@@ -508,7 +509,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(7)
#define SPI_NOR_NO_FR BIT(8)
- u8 no_sfdp_flags;
+ u16 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
#define SECT_4K BIT(1)
#define SPI_NOR_DUAL_READ BIT(3)
@@ -516,6 +517,8 @@ struct flash_info {
#define SPI_NOR_OCTAL_READ BIT(5)
#define SPI_NOR_OCTAL_DTR_READ BIT(6)
#define SPI_NOR_OCTAL_DTR_PP BIT(7)
+#define SPI_NOR_OCTAL_STR_READ BIT(8)
+#define SPI_NOR_OCTAL_STR_PP BIT(9)
u8 fixup_flags;
#define SPI_NOR_4B_OPCODES BIT(0)