diff mbox series

[26/30] selftests/rseq: x86: Implement rseq_load_u32_u32

Message ID	20221122203932.231377-27-mathieu.desnoyers@efficios.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> To: Peter Zijlstra <peterz@infradead.org> Cc: linux-kernel@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>, "Paul E . McKenney" <paulmck@kernel.org>, Boqun Feng <boqun.feng@gmail.com>, "H . Peter Anvin" <hpa@zytor.com>, Paul Turner <pjt@google.com>, linux-api@vger.kernel.org, Christian Brauner <brauner@kernel.org>, Florian Weimer <fw@deneb.enyo.de>, David.Laight@ACULAB.COM, carlos@redhat.com, Peter Oskolkov <posk@posk.io>, Alexander Mikhalitsyn <alexander@mihalicyn.com>, Chris Kennelly <ckennelly@google.com>, Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Subject: [PATCH 26/30] selftests/rseq: x86: Implement rseq_load_u32_u32 Date: Tue, 22 Nov 2022 15:39:28 -0500 Message-Id: <20221122203932.231377-27-mathieu.desnoyers@efficios.com> In-Reply-To: <20221122203932.231377-1-mathieu.desnoyers@efficios.com> References: <20221122203932.231377-1-mathieu.desnoyers@efficios.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	RSEQ node id and mm concurrency id extensions \| [00/30] RSEQ node id and mm concurrency id extensions [01/30] selftests/rseq: Fix: Fail thread registration when CONFIG_RSEQ=n [02/30] rseq: Introduce feature size and alignment ELF auxiliary vector entries [03/30] rseq: Introduce extensible rseq ABI [04/30] rseq: Extend struct rseq with numa node id [05/30] selftests/rseq: Use ELF auxiliary vector for extensible rseq [06/30] selftests/rseq: Implement rseq numa node id field selftest [07/30] sched: Introduce per-memory-map concurrency ID [08/30] rseq: Extend struct rseq with per-memory-map concurrency ID [09/30] selftests/rseq: Remove RSEQ_SKIP_FASTPATH code [10/30] selftests/rseq: Implement rseq mm_cid field support [11/30] selftests/rseq: x86: Template memory ordering and percpu access mode [12/30] selftests/rseq: arm: Template memory ordering and percpu access mode [13/30] selftests/rseq: arm64: Template memory ordering and percpu access mode [14/30] selftests/rseq: mips: Template memory ordering and percpu access mode [15/30] selftests/rseq: ppc: Template memory ordering and percpu access mode [16/30] selftests/rseq: s390: Template memory ordering and percpu access mode [17/30] selftests/rseq: riscv: Template memory ordering and percpu access mode [18/30] selftests/rseq: Implement basic percpu ops mm_cid test [19/30] selftests/rseq: Implement parametrized mm_cid test [20/30] selftests/rseq: parametrized test: Report/abort on negative concurrency ID [21/30] tracing/rseq: Add mm_cid field to rseq_update [22/30] lib: Implement find_{first,next,nth}_notandnot_bit, find_first_andnot_bit [23/30] cpumask: Implement cpumask_{first,next}_{not,}andnot [24/30] sched: NUMA-aware per-memory-map concurrency ID [25/30] rseq: Extend struct rseq with per-memory-map NUMA-aware Concurrency ID [26/30] selftests/rseq: x86: Implement rseq_load_u32_u32 [27/30] selftests/rseq: Implement mm_numa_cid accessors in headers [28/30] selftests/rseq: Implement numa node id vs mm_numa_cid invariant test [29/30] selftests/rseq: Implement mm_numa_cid tests [30/30] tracing/rseq: Add mm_numa_cid field to rseq_update

Commit Message

Mathieu Desnoyers Nov. 22, 2022, 8:39 p.m. UTC

  Allow loading a pair of u32 within a rseq critical section. It can be
used in situations where both rseq_abi()->mm_numa_cid and
rseq_abi()->node_id need to be sampled atomically with respect to
preemption, signal delivery and migration.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
---
 tools/testing/selftests/rseq/rseq-x86-bits.h | 43 ++++++++++++++++++++
 tools/testing/selftests/rseq/rseq.h          | 14 +++++++
 2 files changed, 57 insertions(+)

diff mbox series

Patch

diff --git a/tools/testing/selftests/rseq/rseq-x86-bits.h b/tools/testing/selftests/rseq/rseq-x86-bits.h
index 8a9431eec467..fdf5ef398393 100644
--- a/tools/testing/selftests/rseq/rseq-x86-bits.h
+++ b/tools/testing/selftests/rseq/rseq-x86-bits.h
@@ -990,4 +990,47 @@  int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t
 
 #endif
 
+#if defined(RSEQ_TEMPLATE_CPU_ID_NONE) && defined(RSEQ_TEMPLATE_MO_RELAXED)
+
+#define RSEQ_ARCH_HAS_LOAD_U32_U32
+
+static inline __attribute__((always_inline))
+int RSEQ_TEMPLATE_IDENTIFIER(rseq_load_u32_u32)(uint32_t *dst1, uint32_t *src1,
+		      uint32_t *dst2, uint32_t *src2)
+{
+	RSEQ_INJECT_C(9)
+
+	__asm__ __volatile__ goto (
+		RSEQ_ASM_DEFINE_TABLE(3, 1f, 2f, 4f) /* start, commit, abort */
+		/* Start rseq by storing table entry pointer into rseq_cs. */
+		RSEQ_ASM_STORE_RSEQ_CS(1, 3b, RSEQ_ASM_TP_SEGMENT:RSEQ_CS_OFFSET(%[rseq_offset]))
+		RSEQ_INJECT_ASM(3)
+		"movl %[src1], %%eax\n\t"
+		"movl %%eax, %[dst1]\n\t"
+		"movl %[src2], %%eax\n\t"
+		"movl %%eax, %[dst2]\n\t"
+		"2:\n\t"
+		RSEQ_INJECT_ASM(4)
+		RSEQ_ASM_DEFINE_ABORT(4, "", abort)
+		: /* gcc asm goto does not allow outputs */
+		: [rseq_offset]		"r" (rseq_offset),
+		  /* final store input */
+		  [dst1]		"m" (*dst1),
+		  [src1]		"m" (*src1),
+		  [dst2]		"m" (*dst2),
+		  [src2]		"m" (*src2)
+		: "memory", "cc", "rax"
+		  RSEQ_INJECT_CLOBBER
+		: abort
+	);
+	rseq_after_asm_goto();
+	return 0;
+abort:
+	rseq_after_asm_goto();
+	RSEQ_INJECT_FAILED
+	return -1;
+}
+
+#endif /* defined(RSEQ_TEMPLATE_CPU_ID_NONE) && defined(RSEQ_TEMPLATE_MO_RELAXED) */
+
 #include "rseq-bits-reset.h"
diff --git a/tools/testing/selftests/rseq/rseq.h b/tools/testing/selftests/rseq/rseq.h
index d7364ea4d201..b6095c2a5da6 100644
--- a/tools/testing/selftests/rseq/rseq.h
+++ b/tools/testing/selftests/rseq/rseq.h
@@ -381,4 +381,18 @@  int rseq_cmpeqv_trymemcpy_storev(enum rseq_mo rseq_mo, enum rseq_percpu_mode per
 	}
 }
 
+#ifdef RSEQ_ARCH_HAS_LOAD_U32_U32
+
+static inline __attribute__((always_inline))
+int rseq_load_u32_u32(enum rseq_mo rseq_mo,
+		      uint32_t *dst1, uint32_t *src1,
+		      uint32_t *dst2, uint32_t *src2)
+{
+	if (rseq_mo != RSEQ_MO_RELAXED)
+		return -1;
+	return rseq_load_u32_u32_relaxed(dst1, src1, dst2, src2);
+}
+
+#endif
+
 #endif  /* RSEQ_H_ */