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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id j10-20020adff00a000000b002d1bfe3269esm27102109wro.59.2023.03.28.02.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 02:05:01 -0700 (PDT) From: Alexandre Mergnat Date: Tue, 28 Mar 2023 11:04:47 +0200 Subject: [PATCH v6 1/2] arm64: dts: mediatek: add i2c support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20221122-mt8365-i2c-support-v6-1-e1009c8afd53@baylibre.com> References: <20221122-mt8365-i2c-support-v6-0-e1009c8afd53@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v6-0-e1009c8afd53@baylibre.com> To: Qii Wang , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , Rob Herring , AngeloGioacchino Del Regno , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2696; i=amergnat@baylibre.com; h=from:subject:message-id; bh=751COW4mlyt6NiZw3ZmEVilTCKVZTkOYnz6i1pHU/mc=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkIq27A//D5eTADCDZW5waqfVl8NWE1cZPKo7QzgiC QRY+qwWJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCKtuwAKCRArRkmdfjHURdKcD/ 9dklIQyjq2bmzwRR1bmW/+ucAFmmdbP+ueL5/JvJgO2UYTKs0dAUjRvVeAlRUimE/+1PRxlG9vmw6R W2HSHcsx2m0stXGqwqLUeSGoO7VO61cHl3CD4ksm1sw8BIXkGee+9guQwuCpvm+G43Qik20amAVn4k 76j5WjfNGANer3cuTkBqFfcI2EpUy8G51UfKyfoBvHmy543aR0A8gccs4fptpVkcYqS7QF3q0xku9V Tb7icnO+irswsZGNe90mnAdzUPWf4cDlcLPH2AnddCHJ8F1jpeM804/cxzzi5zs51IL7hkg54TvkB8 4e+1jWeV64d5BxhUL+rcnRE0S9AsovOq+X+Nc7Vfr7sLnjTMCwojclLcQ9I03fRNJ5fAGs1x5uMzfR V8DSU3Xgzt5BcFjDbFjHIJf31Y9UgMWLexRz41gJcaiudvPPK0B9gjsEij78LnLoQD5O40Au45+hpv nDJOX7PHM5GrzSw0aowSIFZQVmmAb1I7JqHZqmUh4UijJf/czUMi95xVmQ6neBEAhwc0/2qy1g7f0J B5vqq34XX/Iyr08yVdl2oU/TW0V5AM6uA4gnsVQuBwMnCSc1QnDhuRbtf/7tdU5TDpvtaxomYodWa0 IE9TZtRb0iZR3iJBvgH+rRojySvGge/iZb2iWhmSnG8LnJfQRT3RZuD3Jniw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761601960789436533?= X-GMAIL-MSGID: =?utf-8?q?1761601960789436533?= There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 15ac4c1f0966..b70f4d256f63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,42 @@ pwm: pwm@11006000 { clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi: spi@1100a000 { compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg = <0 0x1100a000 0 0x100>; @@ -295,6 +331,18 @@ spi: spi@1100a000 { status = "disabled"; }; + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ssusb: usb@11201000 { compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;