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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 14-20020a63020e000000b00460b3aecba3si3269300pgc.542.2022.11.18.01.44.51; Fri, 18 Nov 2022 01:45:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass (test mode) header.i=@ideasonboard.com header.s=mail header.b=VjuiMCyb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242072AbiKRJlI (ORCPT + 99 others); Fri, 18 Nov 2022 04:41:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242076AbiKRJkh (ORCPT ); Fri, 18 Nov 2022 04:40:37 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DCD59BA20; Fri, 18 Nov 2022 01:40:15 -0800 (PST) Received: from pyrite.tail37cf.ts.net (h175-177-042-159.catv02.itscom.jp [175.177.42.159]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 0F972AF4; Fri, 18 Nov 2022 10:40:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1668764414; bh=X2F049y6ifOJorIVcdIpGUTYOZmf5YdHHHoNUmErehQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VjuiMCybJMFoRFZIl0gbx3zzpJg/rSCBzua0frEYoiHda4fAflNAANRHWz8IYW6yi 5yhcbUBSUJdc2aCfhU8anf1dUfAMu/U5iIJgd6SYuD9jzATf5xJ+klY4u4gDDtro/N mQbQIduKJutHXDZvaEu7nhJc/qik+8CNcLaoeQuo= From: Paul Elder To: linux-media@vger.kernel.org Cc: Paul Elder , Dafna Hirschfeld , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Helen Koike , Laurent Pinchart , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/14] media: rkisp1: Add i.MX8MP-specific registers for MI and resizer Date: Fri, 18 Nov 2022 18:39:25 +0900 Message-Id: <20221118093931.1284465-9-paul.elder@ideasonboard.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118093931.1284465-1-paul.elder@ideasonboard.com> References: <20221118093931.1284465-1-paul.elder@ideasonboard.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749826618621954257?= X-GMAIL-MSGID: =?utf-8?q?1749826618621954257?= Add register definitions for resizer format conversion control and for the memory interface output that are specific to the ISP version in the i.MX8MP. Signed-off-by: Laurent Pinchart Signed-off-by: Paul Elder --- Changes since v2: - Add missing newlines --- .../platform/rockchip/rkisp1/rkisp1-regs.h | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h index ed34c752be99..6597c563f892 100644 --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h @@ -171,6 +171,23 @@ /* RSZ_CROP_[XY]_DIR */ #define RKISP1_CIF_RSZ_CROP_XY_DIR(start, end) ((end) << 16 | (start) << 0) +/* RSZ_FORMAT_CONV_CTRL */ +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_INPUT_FORMAT_YCBCR_400 (0 << 0) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_INPUT_FORMAT_YCBCR_420 (1 << 0) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_INPUT_FORMAT_YCBCR_422 (2 << 0) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_INPUT_FORMAT_YCBCR_444 (3 << 0) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_OUTPUT_FORMAT_YCBCR_400 (0 << 2) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_OUTPUT_FORMAT_YCBCR_420 (1 << 2) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_OUTPUT_FORMAT_YCBCR_422 (2 << 2) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_OUTPUT_FORMAT_YCBCR_444 (3 << 2) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_CFG_Y_FULL BIT(5) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_CFG_CBCR_FULL BIT(6) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_CFG_422NOCOSITED BIT(7) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_DATA_WIDTH_10_BIT_ENABLE BIT(8) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_DATA_WIDTH_10_BIT_METHOD BIT(9) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_PACK_FORMAT_PLANAR (0 << 10) +#define RKISP1_CIF_RSZ_FORMAT_CONV_CTRL_RSZ_PACK_FORMAT_SEMI_PLANAR (1 << 10) + /* MI_IMSC - MI_MIS - MI_RIS - MI_ICR - MI_ISR */ #define RKISP1_CIF_MI_FRAME(stream) BIT((stream)->id) #define RKISP1_CIF_MI_MBLK_LINE BIT(2) @@ -213,6 +230,24 @@ #define RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1) #define RKISP1_CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2) +/* MI_OUTPUT_ALIGN_FORMAT */ +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT BIT(0) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES BIT(1) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_WORDS BIT(2) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_DWORDS BIT(3) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES BIT(4) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_WORDS BIT(5) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_DWORDS BIT(6) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_DMA_BYTE_SWAP_BYTES BIT(7) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_DMA_BYTE_SWAP_WORDS BIT(8) +#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_DMA_BYTE_SWAP_DWORDS BIT(9) + +/* MI_MP_OUTPUT_FIFO_SIZE */ +#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_FULL (0 << 0) +#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_HALF (1 << 0) +#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_QUARTER (2 << 0) +#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_EIGHT (3 << 0) + /* VI_CCL */ #define RKISP1_CIF_CCL_CIF_CLK_DIS BIT(2) /* VI_ISP_CLK_CTRL */