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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v25-20020a637a19000000b0047715878e0dsi86573pgc.298.2022.11.17.03.10.32; Thu, 17 Nov 2022 03:10:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=R+iJ5Cvo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239667AbiKQLJG (ORCPT + 99 others); Thu, 17 Nov 2022 06:09:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239848AbiKQLII (ORCPT ); Thu, 17 Nov 2022 06:08:08 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 317095C74F; Thu, 17 Nov 2022 03:08:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668683282; x=1700219282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RK+XGHZ2BELVVYkxCYeGM6RfxC8qsuOPoluHIaCRq2s=; b=R+iJ5Cvo2Mki1IeRdhrlzG7Eu5NnQ6aEVYbVUCy5L5fXluZerCkwd8+r 9GKChPwrLeju5+dy0T2TNJEOYx4hEipV+XDBKjJ0Y7f0USWzipBfXaYwX UkePNZBJsMYmb3KNSvaUhyz/VEgNbkbvogjM5YktSTtS/4jz5MkIv0h7f aFgZK/vLqxrZ+GVl9qBX18+VPsvA//poqAN2x5IdiyR1tzvkEt1pdVft4 VtFdOdTwItiEwicb61V/M7J+H6dYr9wXUQbY3q2MRYYXN0QA3dQYC+qJd JFk7bSukzzWKIinkCLEsPpQi6Q4EodErZSImjf8b6hPLRt9rSDUN9BSIr Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="314638732" X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="314638732" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2022 03:08:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="617572346" X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="617572346" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga006.jf.intel.com with ESMTP; 17 Nov 2022 03:07:59 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 99CDF2B7; Thu, 17 Nov 2022 13:08:24 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig?= , Hans de Goede , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v5 7/7] pinctrl: intel: Enumerate PWM device when community has a capability Date: Thu, 17 Nov 2022 13:08:06 +0200 Message-Id: <20221117110806.65470-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221117110806.65470-1-andriy.shevchenko@linux.intel.com> References: <20221117110806.65470-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749741412825725902?= X-GMAIL-MSGID: =?utf-8?q?1749741412825725902?= Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko Acked-by: Thierry Reding Reviewed-by: Mika Westerberg Acked-by: Linus Walleij Acked-by: Uwe Kleine-König --- drivers/pinctrl/intel/pinctrl-intel.c | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 52ecd66ce357..d74c8b650aa7 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -21,6 +21,8 @@ #include #include +#include + #include "../core.h" #include "pinctrl-intel.h" @@ -46,6 +48,8 @@ #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) #define PADOWN_GPP(p) ((p) / 8) +#define PWMC 0x204 + /* Offset from pad_regs */ #define PADCFG0 0x000 #define PADCFG0_RXEVCFG_SHIFT 25 @@ -1499,6 +1503,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) return 0; } +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, + struct intel_community *community) +{ + static const struct pwm_lpss_boardinfo info = { + .clk_rate = 19200000, + .npwm = 1, + .base_unit_bits = 22, + .bypass = true, + }; + struct pwm_lpss_chip *pwm; + + if (!(community->features & PINCTRL_FEATURE_PWM)) + return 0; + + if (!IS_REACHABLE(CONFIG_PWM_LPSS)) + return 0; + + pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); + return PTR_ERR_OR_ZERO(pwm); +} + static int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { @@ -1584,6 +1609,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev, ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); if (ret) return ret; + + ret = intel_pinctrl_probe_pwm(pctrl, community); + if (ret) + return ret; } irq = platform_get_irq(pdev, 0);