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[2620:137:e000::1:20]) by mx.google.com with ESMTP id oc3-20020a17090b1c0300b002130053cad7si4977216pjb.7.2022.11.17.02.56.03; Thu, 17 Nov 2022 02:56:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=uwYiwXed; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239696AbiKQKyY (ORCPT + 99 others); Thu, 17 Nov 2022 05:54:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239267AbiKQKxV (ORCPT ); Thu, 17 Nov 2022 05:53:21 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6AD55BD4C; Thu, 17 Nov 2022 02:53:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682399; x=1700218399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pub4+zHZreJmfMrR4t0OMZDURmCLD6tCvA9jmlzzuIg=; b=uwYiwXedumA2nE/77X4Fiu9LAmA9GY0Q979vmoG6/GVq/gaXV8AunBRD wI5SsCNe3RRM6cBBHBiHVuf0dXSibP322sUfS8YDiMrMPO4BF4Fzg1iLC 849cP+4de408Rof3pPXHfX4x2ZkKxwUKJRe7xreItgs9ZS3JRiihOibIL kDlzhZyvxoX313YH86W/ugUcdsHd7SbjwbIy/Ta/noj0Yg3UFyfL7qksy JxN0jhtEitDaSQGRTsNTDegH3ZMsbGcQ9O//0n3jwuRSyh1CtqlwD3PVu o0pPOqu6abGC4XUNZQLNTeoTCy2Y73Cp3ve+SuYR923StvaSwtmVpxt2h A==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965652" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:14 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:12 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 7/8] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:48 +0200 Message-ID: <20221117105249.115649-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749740501540782133?= X-GMAIL-MSGID: =?utf-8?q?1749740501540782133?= sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index dd1dec9d4e07..ffd9627874c9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -669,7 +669,8 @@ flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read;