[v3,1/5] cpufreq: amd-pstate: cpufreq: amd-pstate: reset MSR_AMD_PERF_CTL register at init
Message ID | 20221117073541.3350600-2-Perry.Yuan@amd.com |
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State | New |
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Thu, 17 Nov 2022 01:36:08 -0600 From: Perry Yuan <Perry.Yuan@amd.com> To: <rafael.j.wysocki@intel.com>, <ray.huang@amd.com>, <viresh.kumar@linaro.org>, <Mario.Limonciello@amd.com> CC: <Nathan.Fontenot@amd.com>, <Alexander.Deucher@amd.com>, <Deepak.Sharma@amd.com>, <Shimmer.Huang@amd.com>, <Li.Meng@amd.com>, <Xiaojian.Du@amd.com>, <wyes.karny@amd.com>, <gautham.shenoy@amd.com>, <ananth.narayan@amd.com>, <linux-pm@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <stable@vger.kernel.org>, Perry Yuan <Perry.Yuan@amd.com> Subject: [PATCH v3 1/5] cpufreq: amd-pstate: cpufreq: amd-pstate: reset MSR_AMD_PERF_CTL register at init Date: Thu, 17 Nov 2022 15:35:37 +0800 Message-ID: <20221117073541.3350600-2-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117073541.3350600-1-Perry.Yuan@amd.com> References: <20221117073541.3350600-1-Perry.Yuan@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|SA0PR12MB4573:EE_ X-MS-Office365-Filtering-Correlation-Id: d1046258-238a-4416-57aa-08dac86e67cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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AMD Pstate driver Urgent Change
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Commit Message
Yuan, Perry
Nov. 17, 2022, 7:35 a.m. UTC
From: Wyes Karny <wyes.karny@amd.com> MSR_AMD_PERF_CTL is guaranteed to be 0 on a cold boot. However, on a kexec boot, for instance, it may have a non-zero value (if the cpu was in a non-P0 Pstate). In such cases, the cores with non-P0 Pstates at boot will never be pushed to P0, let alone boost frequencies. Kexec is a common workflow for reboot on Linux and this creates a regression in performance. Fix it by explicitly setting the MSR_AMD_PERF_CTL to 0 during amd_pstate driver init. Cc: stable@vger.kernel.org Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> --- drivers/cpufreq/amd-pstate.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ace7d50cf2ac..d844c6f97caf 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -424,12 +424,22 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata) amd_pstate_driver.boost_enabled = true; } +static void amd_perf_ctl_reset(unsigned int cpu) +{ + wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; struct device *dev; struct amd_cpudata *cpudata; + /* + * Resetting PERF_CTL_MSR will put the CPU in P0 frequency, + * which is ideal for initialization process. + */ + amd_perf_ctl_reset(policy->cpu); dev = get_cpu_device(policy->cpu); if (!dev) return -ENODEV;