From patchwork Wed Nov 16 05:15:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolu Lu X-Patchwork-Id: 20718 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3102423wru; Tue, 15 Nov 2022 21:30:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf5X3phK3HFmR1zgUi/mD5LISOLY5FvjwxuBNqPnEALiiZjThJNS0hqkAEOaJgUrjhNramPC X-Received: by 2002:a63:fe51:0:b0:459:a339:89e0 with SMTP id x17-20020a63fe51000000b00459a33989e0mr19208672pgj.300.1668576643937; Tue, 15 Nov 2022 21:30:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668576643; cv=none; d=google.com; s=arc-20160816; b=nJh50PSVQDR9V3/Tf6J1Xv7mrKjh1jJiBKO10ap4xjMPP/9DjGss0WKM9+cS8oprb0 XDhRE1uxQ8E+j4bbGOO6wWdzTOwOtp2WAesxtCoKj8iwSyvOvQNdcGGiMZZqlpV8PQ1T 9VYHKwtEyVyVBouefK6W4A2URp4muUO8ukbQzauky5nefh9Dtw+S3ZpxFRg+UPXg81o/ heuvjgFPOAefwh0H1erHGMq1vDSt7ta42AzjQJIpT2CC0TjAmRfNb3EyFn73dsnYMfaF n1b0z2yTnvzIve5t1MPoCFupMe9QL2U1Cp7K/nsGkerNvAwfCZ7USKGdS728LLSX4NjE k2NA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qYYhMQFTPHtYrbMvv8ueYZfaURudqyN9JVrYp/uZJcI=; b=JqsjaItRuzZeVqXcDvgBf5IOP3zJmqtNl/TOY5pfz1wTHPM8vyehgrv4A6fEuujQyZ qX+tQZnfk5byAA83Oo2y6v+udJdIEmpdNIfVmzw6/fGkuL5atDiULLCyB+vNDtHsK1E7 1+Apa1/lwAHfw60FMUnU84befFu8d184uy6+iqYeypRKEKwnqpDNAtqYp3R7rlQ2OpgM Rh0PknqFUHbuifdmHoAvBis1hNvu5QbDbDOU58VtVx0YnjsEFUqBWm+VbGxtMXqid4TV 62JFamCIOKOPkAI3KgjFyKeoLeKFVW7d0RdhBdumHkIdmCRCGZupuwMzRXWZWiQynYa0 qaXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=X0oXQSx7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 5-20020a170902c24500b00172f8a4b3e1si12565651plg.81.2022.11.15.21.30.30; Tue, 15 Nov 2022 21:30:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=X0oXQSx7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231270AbiKPFWx (ORCPT + 99 others); Wed, 16 Nov 2022 00:22:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230124AbiKPFWp (ORCPT ); Wed, 16 Nov 2022 00:22:45 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6716DBF51 for ; Tue, 15 Nov 2022 21:22:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668576164; x=1700112164; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N39zYywKGtvDLEpu4Wp5yD2tKhZZrUwiZr6H+Wm2BCU=; b=X0oXQSx7JDizAYLFsguIFQi5sRfofbCAxxpoZZN83dpIz8hXTgFOPfCB aWdmfBPcCVT3ZVyCsUOFAcxgHxJOYNjlyrbz6+rDmR7LWu0c+6r2pGNQo LIMGhcBwfnCfXj6tVsVE/lNJAMiebGeFqrpfuNSKTiMvmpvm09zlC9L2n ANJnWGUhzzxI7JK2GnSLBSLLx8wuVkhYNY2Uapa5zlCyR4LxdalBI3M+3 gfcEuriH3jz/N+lXKdKKorH0MYDYHHPG8d/fuWUav3afc7kdWGRL9Gylx kHBKNaZO7ssdJX/FJzne7+f5SBb1DL6KUbe6kjiI+Kew/EUgraqLHeMLV A==; X-IronPort-AV: E=McAfee;i="6500,9779,10532"; a="299982696" X-IronPort-AV: E=Sophos;i="5.96,167,1665471600"; d="scan'208";a="299982696" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2022 21:22:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10532"; a="702724781" X-IronPort-AV: E=Sophos;i="5.96,167,1665471600"; d="scan'208";a="702724781" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga008.fm.intel.com with ESMTP; 15 Nov 2022 21:22:42 -0800 From: Lu Baolu To: Joerg Roedel Cc: Tina Zhang , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] iommu/vt-d: Set SRE bit only when hardware has SRS cap Date: Wed, 16 Nov 2022 13:15:44 +0800 Message-Id: <20221116051544.26540-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221116051544.26540-1-baolu.lu@linux.intel.com> References: <20221116051544.26540-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749629422643726296?= X-GMAIL-MSGID: =?utf-8?q?1749629422643726296?= From: Tina Zhang SRS cap is the hardware cap telling if the hardware IOMMU can support requests seeking supervisor privilege or not. SRE bit in scalable-mode PASID table entry is treated as Reserved(0) for implementation not supporting SRS cap. Checking SRS cap before setting SRE bit can avoid the non-recoverable fault of "Non-zero reserved field set in PASID Table Entry" caused by setting SRE bit while there is no SRS cap support. The fault messages look like below: DMAR: DRHD: handling fault status reg 2 DMAR: [DMA Read NO_PASID] Request device [00:0d.0] fault addr 0x1154e1000 [fault reason 0x5a] SM: Non-zero reserved field set in PASID Table Entry Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table interface") Cc: stable@vger.kernel.org Signed-off-by: Tina Zhang Link: https://lore.kernel.org/r/20221115070346.1112273-1-tina.zhang@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index c30ddac40ee5..e13d7e5273e1 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -642,7 +642,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, * Since it is a second level only translation setup, we should * set SRE bit as well (addresses are expected to be GPAs). */ - if (pasid != PASID_RID2PASID) + if (pasid != PASID_RID2PASID && ecap_srs(iommu->ecap)) pasid_set_sre(pte); pasid_set_present(pte); spin_unlock(&iommu->lock); @@ -685,7 +685,8 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu, * We should set SRE bit as well since the addresses are expected * to be GPAs. */ - pasid_set_sre(pte); + if (ecap_srs(iommu->ecap)) + pasid_set_sre(pte); pasid_set_present(pte); spin_unlock(&iommu->lock);