From patchwork Tue Nov 15 14:40:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 20408 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2767399wru; Tue, 15 Nov 2022 06:42:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf47Sktqh3Di0cN+7RNn5TZwCquX6GKVuYnpjfijnP8L3WRkMkOzmdkJZXPcIUuAxmC3QmnP X-Received: by 2002:a17:906:46c4:b0:7ac:db40:7e1 with SMTP id k4-20020a17090646c400b007acdb4007e1mr14471340ejs.204.1668523372664; Tue, 15 Nov 2022 06:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668523372; cv=none; d=google.com; s=arc-20160816; b=pZCyrrTMYubigxrMYMSNxIRPO9UXlKYUQgRi8sRG8FRdbE171ngfKt5lOTMBzwwLUw ZuZJoyqCWcfp4hZ41azCushsDsd7eYzuL3pehQTgFnMz6+Ufi0SFm8a2n/N57+LagDqb YVL/imScSEqXiiesYP6oMQC2+6FElFoUCHNaDW3I7P5U1E5DPx4Z+3G5hoPkM30Dj2if HzJl50fjRqyEmlQPsNwgLl4+1wgVGMyNiqKZmDrwIU2+oP4+GZq3RLU0P6wNgjXIVDXj NpBm/m/GhBt7zuVasWgboC1ETruV8j4BOKOFd/1Xk5L/A1q4FQpRp9s9itFDMvvScHR6 PLUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/6Vv/w6K9zCywBrFk9RRx+pxCDVSaRfGScSd0vKKCiY=; b=yFcQzAkBYIzQpM+tNFkVBact+nuNOwzcJnWYlhWKe4FVTcoeoCc9iAJ0VzRN62oJPM UZpGP+h62YLjwhy/s8l+viqdFA5NDoCACV4Bl0fh2TEXDYLkct0XsTdWHwJ3fl5K4Adm nk2A33jn5NA8RRj0S8X4AE4RTExh5ooG4YOdqob4/Apjn4G5ij3MSP4b8cpLuqFBx6Zy 73Vp5Wszn7VcsUxsK7siMpyFccvFT412I8M1+MI8Qq1kMy43cvlUJxV7v9AEbLS5Ttgg IUQa8c79y+2Eugi8y96bk42JQZ6kzM2DY5hLgH3a0Zs6v/ZNmJlLRlWnBKcp6XH6ZTlB FDuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Mf5uFpFy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dk22-20020a170906f0d600b007aa8a5131a3si8545193ejb.181.2022.11.15.06.42.25; Tue, 15 Nov 2022 06:42:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Mf5uFpFy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238039AbiKOOla (ORCPT + 99 others); Tue, 15 Nov 2022 09:41:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232197AbiKOOk4 (ORCPT ); Tue, 15 Nov 2022 09:40:56 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AE932A24C; Tue, 15 Nov 2022 06:40:55 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D5FE4617E1; Tue, 15 Nov 2022 14:40:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 29BCFC4FF1F; Tue, 15 Nov 2022 14:40:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668523253; bh=S2uFsZNL8KCSy0MjdXARA3YnKzPzvstaWp9vcv8/aFY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Mf5uFpFymnYFkN0eVTFtnJ0vZRjvBTeDjQ2QP4hABjB0tvWpC8z1quUHeUKUcdsQ5 F2pQ+zo3NRRYF6NhMddbjcwOfY5f1DypYXsstQH23oxwDpEUdVDmFDSgvZsirQDXhg lNonDDM0JDmWBFFh2+CKPY5jc9S3SvvapCxYF8BNkNJz0Ye8NbEwA5mUIFMqQqnxFq E6kHILwQ22xa4hekw2yKUiZq2iEH+3c0vPxchUatRtjLtEBItyIPwm71K8Mdw90VoL fE3TjW4cec/lAcM9sDjwBOwbdDyXkPPklvqHnWtXAAW1u+nvrb0ac7CZDbsIHsxpUd UmqtidQw+vk3A== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oux6t-0000g9-NW; Tue, 15 Nov 2022 15:40:23 +0100 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 15/15] arm64: dts: qcom: sc8280xp: fix USB-DP PHY nodes Date: Tue, 15 Nov 2022 15:40:05 +0100 Message-Id: <20221115144005.2478-16-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221115144005.2478-1-johan+linaro@kernel.org> References: <20221115144005.2478-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749573564145386461?= X-GMAIL-MSGID: =?utf-8?q?1749573564145386461?= Update the USB4-USB3-DP QMP PHY nodes to match the new binding which specifically includes the missing register regions (e.g. DP_PHY) and allows for supporting DisplayPort Alternate Mode. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++------------------ 1 file changed, 23 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 85c674e7e1a5..3c5bc56e68fc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -763,7 +764,7 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <&usb_0_ssphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -771,7 +772,7 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <&usb_1_ssphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -1666,42 +1667,26 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; - usb_0_qmpphy: phy-wrapper@88ec000 { + usb_0_qmpphy: phy@88eb000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; - reg = <0 0x088ec000 0 0x1e4>, - <0 0x088eb000 0 0x40>, - <0 0x088ed000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x088eb000 0 0x4000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB4_EUD_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - power-domains = <&gcc USB30_PRIM_GDSC>; + #clock-cells = <1>; + #phy-cells = <1>; status = "disabled"; - - usb_0_ssphy: usb3-phy@88eb400 { - reg = <0 0x088eb400 0 0x100>, - <0 0x088eb600 0 0x3ec>, - <0 0x088ec400 0 0x364>, - <0 0x088eba00 0 0x100>, - <0 0x088ebc00 0 0x3ec>, - <0 0x088ec200 0 0x18>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb0_phy_pipe_clk_src"; - }; }; usb_1_hsphy: phy@8902000 { @@ -1718,42 +1703,26 @@ usb_1_hsphy: phy@8902000 { status = "disabled"; }; - usb_1_qmpphy: phy-wrapper@8904000 { + usb_1_qmpphy: phy@8903000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; - reg = <0 0x08904000 0 0x1e4>, - <0 0x08903000 0 0x40>, - <0 0x08905000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x08903000 0 0x4000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB4_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_SEC_GDSC>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - power-domains = <&gcc USB30_SEC_GDSC>; + #clock-cells = <1>; + #phy-cells = <1>; status = "disabled"; - - usb_1_ssphy: usb3-phy@8903400 { - reg = <0 0x08903400 0 0x100>, - <0 0x08903600 0 0x3ec>, - <0 0x08904400 0 0x364>, - <0 0x08903a00 0 0x100>, - <0 0x08903c00 0 0x3ec>, - <0 0x08904200 0 0x18>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb1_phy_pipe_clk_src"; - }; }; mdss1_dp0_phy: phy@8909a00 { @@ -1941,7 +1910,7 @@ usb_0_dwc3: usb@a600000 { reg = <0 0x0a600000 0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x820 0x0>; - phys = <&usb_0_hsphy>, <&usb_0_ssphy>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; }; @@ -1995,7 +1964,7 @@ usb_1_dwc3: usb@a800000 { reg = <0 0x0a800000 0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x860 0x0>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; };