From patchwork Tue Nov 15 13:30:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 20376 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2729883wru; Tue, 15 Nov 2022 05:33:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf4v/kbaUGB2ryym3v1QLN7snMF5yOdqwS/QhADlLTldd4e9ccz4nkxqrFbgbJlDepb+n0C0 X-Received: by 2002:a63:d156:0:b0:46e:beb0:9d2c with SMTP id c22-20020a63d156000000b0046ebeb09d2cmr16504928pgj.117.1668519212822; Tue, 15 Nov 2022 05:33:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668519212; cv=none; d=google.com; s=arc-20160816; b=Fbznk8aBCvXB4t3u0HS3DdBZ+7IaMJPIx+svjENzEFbpboTJCNws4HNsFCW8W2cc09 Wg0/wNIu3gBB+vJomcMv1TzgxPG3c+OoOb0ltuZEs0Bwc1VQ6TRHT0AZoyEIiWz5Is0Y fJKJjEMYzhd9uW6FPBJ96/agccf86P4KHPuAV9/iQnGe4vJLLFv1BOey61vBmtbkKyl6 7oAXqse0g0zoORFIyOIfjw70QycdxNkQrnBT/yhwRjI4AFpTW0pfzqBo8MG2SlpAxuU3 t5LqleuoF8Ts2Hj3kvubUG1leyrivKhednBVVBE2Om4/JV6wOz4SzIMhDz01hIKKl0Wd 5rcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BI4uKN83KwpFv+aZH8WcfU1uC+N8zfagUkvOFMX2f/0=; b=YRX4+ZCtkkwehdqsPUy0zgGmpEcEPs+RnZYDXu0qtmOg7qYxVQC5vbAMzNMmNKiemq D7UX2SQglhiN7RwsYHTIib5YXb+D2bTNGW44/H41Q0n364p37S9ibCncv8+2pmQBxaMD bWJsgr/BlI3OJ1SeP4fw+ZloEh1ZY3TuL9yTjdzvi6vapXKzhtEem50MO76PI9vjyACJ qKOjQ8i2JZrTIKsMbknJq8Kqn12JR/AQro2T/Z4fuE65R3DK0Gz46F7QUib+ViiT7Zms CzrkCwdiIteeke/XbHVaHf9SWFO7jqQbxWEjyZZZ5DAIWzdQXwpqevB5VaKZJFp9KlxE QY0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="paG/2fJE"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g4-20020a655944000000b0046ff7bbe583si12752366pgu.702.2022.11.15.05.33.17; Tue, 15 Nov 2022 05:33:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="paG/2fJE"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229750AbiKONbQ (ORCPT + 99 others); Tue, 15 Nov 2022 08:31:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbiKONbP (ORCPT ); Tue, 15 Nov 2022 08:31:15 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D84D9E88 for ; Tue, 15 Nov 2022 05:31:13 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id f7so21861134edc.6 for ; Tue, 15 Nov 2022 05:31:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BI4uKN83KwpFv+aZH8WcfU1uC+N8zfagUkvOFMX2f/0=; b=paG/2fJENIvm8NnWAawUhhBzGSPdHRUpmbX4bOrjkAokwgW0r0gNTXCK9Zf+jwsSax k8F1TG1paJuubjAzS5iLwmaEavsKZkxKPlXnDnjEok59ScH5ZjSdN+xtgF6dasadbWXl R/nbD24qHP7qcJ/VBNcX68QJhF60mKMl8CBp1Oxc6oMngar7Uh6Ec427ORMXsM93P1xQ VlTuH6S5YVIScNueY0JEMKkQ1JinpLtVv712a7i/XwL26wZ+aaK+POyI8QMHqxzUkd1F ftru4A7QfO8njAqTbaYU1NgA4Nkvbi6IKQXydF95oYdU225WFkcxZqO0bF4FaLef0XNA JMlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BI4uKN83KwpFv+aZH8WcfU1uC+N8zfagUkvOFMX2f/0=; b=U/HQJV/2cZorUpB3vdfjTq5ngr2VKvg2A4UQTMY8lnbXVkV7H9Kp85K0ShoEkrqrLq /SlgCXPbNLWJ9ojvCH/03Y28glZpSgOMflDsMxvLvAoMPOU76ThJ5bNRfxPft+F7kSZE ISTIlFqJeRZvFYmp5xDqlIvUn4NtQ2rVmv/wCXtchohsfW+wub/rQMjtDBa8w0zj9n5n g3mPirJO8yIlXXo2DJUXFxqmvXAwxaLu4lq/DQSLXu3tVpcrb9rbluieh+XSHCBl1hYT QfvhxruY17YG7oF9JiFV1Ygk8+coUlo/RZ7wB/0z5AkJuhqDLyQYEu9qNb/OgaKq6R08 29MQ== X-Gm-Message-State: ANoB5pnKQq/bl4Xgu7hPqFtzHLWcg7m9YF2TE31yGgQcYuDi4HnZhrX9 i5oJBigZ5yB36L1iys7tWb3YWQ== X-Received: by 2002:aa7:d64a:0:b0:45b:cb6b:c342 with SMTP id v10-20020aa7d64a000000b0045bcb6bc342mr15099503edr.282.1668519072342; Tue, 15 Nov 2022 05:31:12 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id q22-20020aa7d456000000b004618f2127d2sm6162176edr.57.2022.11.15.05.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 05:31:11 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, swboyd@chromium.org, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v2 01/12] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Date: Tue, 15 Nov 2022 14:30:54 +0100 Message-Id: <20221115133105.980877-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115133105.980877-1-robert.foss@linaro.org> References: <20221115133105.980877-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749569201822020497?= X-GMAIL-MSGID: =?utf-8?q?1749569201822020497?= Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml new file mode 100644 index 000000000000..120500395c9a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display DPU + +maintainers: + - Robert Foss + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +...