Message ID | 20221115101122.155440-3-angelogioacchino.delregno@collabora.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2626733wru; Tue, 15 Nov 2022 02:13:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf65vP1VVS+k/x1osXnzUlBm9PERgCpSaAb4Ug1VbsVbkW7NZ7opVnCRdYYoRS7d52y8QPak X-Received: by 2002:a17:906:7707:b0:78d:9324:6f18 with SMTP id q7-20020a170906770700b0078d93246f18mr13753615ejm.664.1668507180572; Tue, 15 Nov 2022 02:13:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668507180; cv=none; d=google.com; s=arc-20160816; b=Oqr77SVE4qng1FRUg9NFtFTqpY2V6lUvjSFMis+tJA/UewridpJEwtHJVP/BcvBeWD 33PrGMSua/eZaQD5ZjVRVk/yaQliWvo6V903PnqsTvGDz1taLxofJ9RKudYZ1Ee6hh68 DECNvGAHxAnrdxVbe0Mmcz4pQME9okI+UnC89PgM7WmzPAA7hJUM0SrQL15CJcXeFZsL INtu+7A5cmLdfh35Qf+kGj7CZKQANy/xWOIS1wlhOOdVOXOwYNIQ83D7P8jUN/Z38jE4 ErflNjWu0tCXMMgwyrmRj/ETwNeLqS7Zjd0t2Rxdx0i3XlPVLsIiptsz4kBw3O0IiLiV pC0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rNJRFw6AnDd4epmr97/KmjVOVTLbs6ewwE3YPdKB3yQ=; b=Ussgexmr+Ze9kWC9Ztg53b6hnGLUX+Vo+Sfjgl46ZZVFZTUIjNhZkq/O5ef4Q3g2Lx GONf5vF/Y/42nA/ZUYHjyNV5ieCogc+QtwRJNFqqUtOfKuMZRPkIZHDA1b5x36TIyYle X+d2KrClCGMqlzS6zRa8lPJcIqbdGwPw+GzPNCStRCecCLLh9QUlHcI0rkGujq9R2/iH iS67uhOOSnb2kTTA2S2zJrejoJILiMK7J848PRkJOmzAbGroPTlFK+brLysgm0WY7NaE w7Ni4dBsxFqH/+WqltD62XRN5aJWNCtTgppCGVEcXj5Ag6OJTSX6jAXlJT7Tra1QS6cr Y0UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=SJr0Wkgo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s2-20020a1709062ec200b0078dc5b2b6c4si8456090eji.666.2022.11.15.02.12.35; Tue, 15 Nov 2022 02:13:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=SJr0Wkgo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238281AbiKOKLp (ORCPT <rfc822;lkml4gm@gmail.com> + 99 others); Tue, 15 Nov 2022 05:11:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238267AbiKOKLh (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 15 Nov 2022 05:11:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9C22F0B; Tue, 15 Nov 2022 02:11:36 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A58C766029AE; Tue, 15 Nov 2022 10:11:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668507095; bh=JcV01OqQI7OdtwJTtMaesEof4OedrSHFsOnwvt1LCKw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SJr0WkgoBF3KvKtN586V/Vto5GR8uIk0+49Hv/W61piKmhFrGjeBxpbKynVBnd07a uVOuvG8PXWxxN4YTTIcExNs1/nMGbpF2TCgaJ7jrhmULnnn1VfRf0yAXhHBwA3aSeD Bytifi64josXifWhvSlgzNsn5yoaanXYHONplATUYvrxIlXAT3qCTSmxLjStbHJsN5 iSPzSXgk//gX1J6aYCAa3O9ZLXIWbdd4cHMjQhyMQJkyO/Bgp3t7edCJx3/G/HAN19 KsHNVRWdR45usbbQtJE0svcbt5DDK4ep99HcOqKt+fDhYRSW8BeHx1SlzRUZMKAZY7 2xDTpNChr6+7g== From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robdclark@gmail.com, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Subject: [PATCH v3 2/6] iommu/qcom: Use the asid read from device-tree if specified Date: Tue, 15 Nov 2022 11:11:18 +0100 Message-Id: <20221115101122.155440-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221115101122.155440-1-angelogioacchino.delregno@collabora.com> References: <20221115101122.155440-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749556585428834335?= X-GMAIL-MSGID: =?utf-8?q?1749556585428834335?= |
Series |
Add support for Qualcomm's legacy IOMMU v2
|
|
Commit Message
AngeloGioacchino Del Regno
Nov. 15, 2022, 10:11 a.m. UTC
As specified in this driver, the context banks are 0x1000 apart but on some SoCs the context number does not necessarily match this logic, hence we end up using the wrong ASID: keeping in mind that this IOMMU implementation relies heavily on SCM (TZ) calls, it is mandatory that we communicate the right context number. Since this is all about how context banks are mapped in firmware, which may be board dependent (as a different firmware version may eventually change the expected context bank numbers), introduce a new property "qcom,ctx-num": when found, the ASID will be forced as read from the devicetree. When "qcom,ctx-num" is not found, this driver retains the previous behavior as to avoid breaking older devicetrees or systems that do not require forcing ASID numbers. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> [Marijn: Rebased over next-20221111] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
Comments
On 15/11/2022 12:11, AngeloGioacchino Del Regno wrote: > As specified in this driver, the context banks are 0x1000 apart but > on some SoCs the context number does not necessarily match this > logic, hence we end up using the wrong ASID: keeping in mind that > this IOMMU implementation relies heavily on SCM (TZ) calls, it is > mandatory that we communicate the right context number. > > Since this is all about how context banks are mapped in firmware, > which may be board dependent (as a different firmware version may > eventually change the expected context bank numbers), introduce a > new property "qcom,ctx-num": when found, the ASID will be forced > as read from the devicetree. > > When "qcom,ctx-num" is not found, this driver retains the previous > behavior as to avoid breaking older devicetrees or systems that do > not require forcing ASID numbers. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > [Marijn: Rebased over next-20221111] > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > index bfd7b51eb5db..491a8093f3d6 100644 > --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c > +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > @@ -551,7 +551,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) > * index into qcom_iommu->ctxs: > */ > if (WARN_ON(asid < 1) || > - WARN_ON(asid > qcom_iommu->num_ctxs)) { > + WARN_ON(asid > qcom_iommu->num_ctxs) || > + WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) { Separate change in my opinion. Please split it to a separate patch with proper Fixes: tag. > put_device(&iommu_pdev->dev); > return -EINVAL; > } > @@ -638,7 +639,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev) > > static int get_asid(const struct device_node *np) > { > - u32 reg; > + u32 reg, val; > + int asid; > > /* read the "reg" property directly to get the relative address > * of the context bank, and calculate the asid from that: > @@ -646,7 +648,17 @@ static int get_asid(const struct device_node *np) > if (of_property_read_u32_index(np, "reg", 0, ®)) > return -ENODEV; > > - return reg / 0x1000; /* context banks are 0x1000 apart */ > + /* > + * Context banks are 0x1000 apart but, in some cases, the ASID > + * number doesn't match to this logic and needs to be passed > + * from the DT configuration explicitly. > + */ > + if (of_property_read_u32(np, "qcom,ctx-num", &val)) > + asid = reg / 0x1000; > + else > + asid = val; As a matter of preference (and logic) I'd have written that as: if (!of_property_read(np, "qcom,ctx-num", &val)) asid = val; else asid = reg / 0x1000; LGTM otherwise > + > + return asid; > } > > static int qcom_iommu_ctx_probe(struct platform_device *pdev)
On 7.03.2023 17:44, Dmitry Baryshkov wrote: > On 15/11/2022 12:11, AngeloGioacchino Del Regno wrote: >> As specified in this driver, the context banks are 0x1000 apart but >> on some SoCs the context number does not necessarily match this >> logic, hence we end up using the wrong ASID: keeping in mind that >> this IOMMU implementation relies heavily on SCM (TZ) calls, it is >> mandatory that we communicate the right context number. >> >> Since this is all about how context banks are mapped in firmware, >> which may be board dependent (as a different firmware version may >> eventually change the expected context bank numbers), introduce a >> new property "qcom,ctx-num": when found, the ASID will be forced >> as read from the devicetree. >> >> When "qcom,ctx-num" is not found, this driver retains the previous >> behavior as to avoid breaking older devicetrees or systems that do >> not require forcing ASID numbers. >> >> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >> [Marijn: Rebased over next-20221111] >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 +++++++++++++++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> index bfd7b51eb5db..491a8093f3d6 100644 >> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> @@ -551,7 +551,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) >> * index into qcom_iommu->ctxs: >> */ >> if (WARN_ON(asid < 1) || >> - WARN_ON(asid > qcom_iommu->num_ctxs)) { >> + WARN_ON(asid > qcom_iommu->num_ctxs) || >> + WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) { > > Separate change in my opinion. Please split it to a separate patch with proper Fixes: tag. > >> put_device(&iommu_pdev->dev); >> return -EINVAL; >> } >> @@ -638,7 +639,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev) >> static int get_asid(const struct device_node *np) >> { >> - u32 reg; >> + u32 reg, val; >> + int asid; >> /* read the "reg" property directly to get the relative address >> * of the context bank, and calculate the asid from that: >> @@ -646,7 +648,17 @@ static int get_asid(const struct device_node *np) >> if (of_property_read_u32_index(np, "reg", 0, ®)) Use platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = res->start or something like this, the current approach relies on #address-cells = <1> Konrad >> return -ENODEV; >> - return reg / 0x1000; /* context banks are 0x1000 apart */ >> + /* >> + * Context banks are 0x1000 apart but, in some cases, the ASID >> + * number doesn't match to this logic and needs to be passed >> + * from the DT configuration explicitly. >> + */ >> + if (of_property_read_u32(np, "qcom,ctx-num", &val)) >> + asid = reg / 0x1000; >> + else >> + asid = val; > > As a matter of preference (and logic) I'd have written that as: > > if (!of_property_read(np, "qcom,ctx-num", &val)) > asid = val; > else > asid = reg / 0x1000; > > LGTM otherwise > >> + >> + return asid; >> } >> static int qcom_iommu_ctx_probe(struct platform_device *pdev) >
Il 07/03/23 17:44, Dmitry Baryshkov ha scritto: > On 15/11/2022 12:11, AngeloGioacchino Del Regno wrote: >> As specified in this driver, the context banks are 0x1000 apart but >> on some SoCs the context number does not necessarily match this >> logic, hence we end up using the wrong ASID: keeping in mind that >> this IOMMU implementation relies heavily on SCM (TZ) calls, it is >> mandatory that we communicate the right context number. >> >> Since this is all about how context banks are mapped in firmware, >> which may be board dependent (as a different firmware version may >> eventually change the expected context bank numbers), introduce a >> new property "qcom,ctx-num": when found, the ASID will be forced >> as read from the devicetree. >> >> When "qcom,ctx-num" is not found, this driver retains the previous >> behavior as to avoid breaking older devicetrees or systems that do >> not require forcing ASID numbers. >> >> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> >> [Marijn: Rebased over next-20221111] >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 +++++++++++++++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> b/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> index bfd7b51eb5db..491a8093f3d6 100644 >> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c >> @@ -551,7 +551,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct >> of_phandle_args *args) >> * index into qcom_iommu->ctxs: >> */ >> if (WARN_ON(asid < 1) || >> - WARN_ON(asid > qcom_iommu->num_ctxs)) { >> + WARN_ON(asid > qcom_iommu->num_ctxs) || >> + WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) { > > Separate change in my opinion. Please split it to a separate patch with proper > Fixes: tag. > This is of_xlate: the array entry at [asid - 1] is always initialized before the introduction of `qcom,ctx-num`, so this is not a separate change and it does not require a Fixes tag, as it is not fixing a previous behavior, but accounting for a new one. >> put_device(&iommu_pdev->dev); >> return -EINVAL; >> } >> @@ -638,7 +639,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev) >> static int get_asid(const struct device_node *np) >> { >> - u32 reg; >> + u32 reg, val; >> + int asid; >> /* read the "reg" property directly to get the relative address >> * of the context bank, and calculate the asid from that: >> @@ -646,7 +648,17 @@ static int get_asid(const struct device_node *np) >> if (of_property_read_u32_index(np, "reg", 0, ®)) >> return -ENODEV; >> - return reg / 0x1000; /* context banks are 0x1000 apart */ >> + /* >> + * Context banks are 0x1000 apart but, in some cases, the ASID >> + * number doesn't match to this logic and needs to be passed >> + * from the DT configuration explicitly. >> + */ >> + if (of_property_read_u32(np, "qcom,ctx-num", &val)) >> + asid = reg / 0x1000; >> + else >> + asid = val; > > As a matter of preference (and logic) I'd have written that as: > > if (!of_property_read(np, "qcom,ctx-num", &val)) > asid = val; > else > asid = reg / 0x1000; > > LGTM otherwise > Will do! Thanks, Angelo P.S.: Sorry for the very late reply. >> + >> + return asid; >> } >> static int qcom_iommu_ctx_probe(struct platform_device *pdev) >
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index bfd7b51eb5db..491a8093f3d6 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -551,7 +551,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) * index into qcom_iommu->ctxs: */ if (WARN_ON(asid < 1) || - WARN_ON(asid > qcom_iommu->num_ctxs)) { + WARN_ON(asid > qcom_iommu->num_ctxs) || + WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) { put_device(&iommu_pdev->dev); return -EINVAL; } @@ -638,7 +639,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev) static int get_asid(const struct device_node *np) { - u32 reg; + u32 reg, val; + int asid; /* read the "reg" property directly to get the relative address * of the context bank, and calculate the asid from that: @@ -646,7 +648,17 @@ static int get_asid(const struct device_node *np) if (of_property_read_u32_index(np, "reg", 0, ®)) return -ENODEV; - return reg / 0x1000; /* context banks are 0x1000 apart */ + /* + * Context banks are 0x1000 apart but, in some cases, the ASID + * number doesn't match to this logic and needs to be passed + * from the DT configuration explicitly. + */ + if (of_property_read_u32(np, "qcom,ctx-num", &val)) + asid = reg / 0x1000; + else + asid = val; + + return asid; } static int qcom_iommu_ctx_probe(struct platform_device *pdev)