From patchwork Mon Nov 14 01:40:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolu Lu X-Patchwork-Id: 19500 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1912988wru; Sun, 13 Nov 2022 17:49:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf7Lc+XtKCwNvVy+Ao7APbkBVJOV+1fNvsxGWgReCWNz4a3ytuaWWFtd1CYCgPxdLC0vqbZy X-Received: by 2002:a17:907:110d:b0:7a9:6107:572a with SMTP id qu13-20020a170907110d00b007a96107572amr8971526ejb.729.1668390584011; Sun, 13 Nov 2022 17:49:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668390584; cv=none; d=google.com; s=arc-20160816; b=0I48DnbIEB6FdwhkKu5mpEsm1HekbmavQhluofUXRRm9rmb45bI2D5nh/A2on06Oa2 aU6kiJRpEguPy9M48CGOcw/NJW7r7lduydKnraKin0fdWFfBkhDxdwVVi9A3+izC3PvP b1pyApGY5P9eV0utDoL9ITcB2C/zW8xQDVq3sRmSfHQTqmhJ0nrHwCwrfD8fifhJzJmY ztrNU+E6V4cdDOFMceLBAaE8mh/IMcKBRyFN3PssbkUcX3YPPZ9sbCHp3m2q4MM2FpOm KZ8HUg2SPZwYeYU3rzkLPmnav6QkaEfnqCph0MakjyieOHYoMNKX7b7zhzu8Y5PdOXr0 10BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=atbQ4D46TR5gbspAkoeRP+L2FElPZsU6Hux5U2N9SE4=; b=c9jFBTiytOSd7mKmiFpNTwqjJCwijJ6LgolwCNfC6Z4uEDvWdgM76X0FEhI7chm2Mv qm8/iBNaHc57ja3/SJlr8wFtuJdpieI8tLyH+A0eB1kzcbvyYagy+invJB8YsNTFZmHH EX3ZI6dDb8o17y4xCT/bP8XsY2u9KNaJy6j4iWb03gIaUHZga4rZ2FqylaKezivMkuyI jqo2+uaG9EcQBFaLKawavs/++OuVaZK+Xrlhy2cpav25MTBWOEQii5SwyZRZ/xHPbuXr 4f/nwn+MW0iYrVfqXpDX1UQQHaPu9DOnr+ZzgJV6N2Hn5oS9SNUFbW9mD98NjOgqGtXP fKIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Mf4GdQbu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i10-20020a0564020f0a00b004622a17f12bsi7549756eda.259.2022.11.13.17.49.20; Sun, 13 Nov 2022 17:49:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Mf4GdQbu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235720AbiKNBsE (ORCPT + 99 others); Sun, 13 Nov 2022 20:48:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235712AbiKNBry (ORCPT ); Sun, 13 Nov 2022 20:47:54 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF17ADF99 for ; Sun, 13 Nov 2022 17:47:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668390472; x=1699926472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7aamF6wGSE378rpzekeRabhg3g404C8LbAS2Hr4cz0g=; b=Mf4GdQbulA6M59HtXAZTbaqR8JCIqPg2Wa6D86Mg/vUmy1ImJST3JqEF 2AJguVdmpJmiyDhWEZaXXG3ZZxgjTPD5U/SX9murcKuviE1sySHvj4rmy BN0+Wa4QqVuCJbfS0PAEyAlltljMLV1C51R0ROLaH9ZE/8KamYvzG4c2B KlLCYRWIXkbZ4ctwtpEUEFG5zqx0qLSUUoMydl3O5Z1CpuW25k2DaGceV QopnrHHvFLLE6qL5YIqSUZ9WSWQh6oULr7J+JqtVEd/elXu+7LDZTeiVk EokazkPVhB2kTRy+7HInVEjsuW5pmyxedGi7hMKsbaqiunp5L7GDoKWjJ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10530"; a="313006687" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="313006687" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 17:47:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10530"; a="707124208" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="707124208" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga004.fm.intel.com with ESMTP; 13 Nov 2022 17:47:49 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Kevin Tian , Will Deacon , Robin Murphy , Liu Yi L , Jacob jun Pan , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 2/7] iommu/vt-d: Add device_block_translation() helper Date: Mon, 14 Nov 2022 09:40:44 +0800 Message-Id: <20221114014049.3959-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221114014049.3959-1-baolu.lu@linux.intel.com> References: <20221114014049.3959-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749434325177642880?= X-GMAIL-MSGID: =?utf-8?q?1749434325177642880?= If domain attaching to device fails, the IOMMU driver should bring the device to blocking DMA state. The upper layer is expected to recover it by attaching a new domain. Use device_block_translation() in the error path of dev_attach to make the behavior specific. The difference between device_block_translation() and the previous dmar_remove_one_dev_info() is that, in the scalable mode, it is the RID2PASID entry instead of context entry being cleared. As a result, enabling PCI capabilities is moved up. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 44 ++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index bc42a2c84e2a..16eeff2f7e19 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -277,7 +277,7 @@ static LIST_HEAD(dmar_satc_units); #define for_each_rmrr_units(rmrr) \ list_for_each_entry(rmrr, &dmar_rmrr_units, list) -static void dmar_remove_one_dev_info(struct device *dev); +static void device_block_translation(struct device *dev); int dmar_disabled = !IS_ENABLED(CONFIG_INTEL_IOMMU_DEFAULT_ON); int intel_iommu_sm = IS_ENABLED(CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON); @@ -1402,7 +1402,7 @@ static void iommu_enable_pci_caps(struct device_domain_info *info) { struct pci_dev *pdev; - if (!info || !dev_is_pci(info->dev)) + if (!dev_is_pci(info->dev)) return; pdev = to_pci_dev(info->dev); @@ -2047,7 +2047,6 @@ static int domain_context_mapping_one(struct dmar_domain *domain, } else { iommu_flush_write_buffer(iommu); } - iommu_enable_pci_caps(info); ret = 0; @@ -2489,7 +2488,7 @@ static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) dev, PASID_RID2PASID); if (ret) { dev_err(dev, "Setup RID2PASID failed\n"); - dmar_remove_one_dev_info(dev); + device_block_translation(dev); return ret; } } @@ -2497,10 +2496,12 @@ static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) ret = domain_context_mapping(domain, dev); if (ret) { dev_err(dev, "Domain context map failed\n"); - dmar_remove_one_dev_info(dev); + device_block_translation(dev); return ret; } + iommu_enable_pci_caps(info); + return 0; } @@ -4111,6 +4112,37 @@ static void dmar_remove_one_dev_info(struct device *dev) info->domain = NULL; } +/* + * Clear the page table pointer in context or pasid table entries so that + * all DMA requests without PASID from the device are blocked. If the page + * table has been set, clean up the data structures. + */ +static void device_block_translation(struct device *dev) +{ + struct device_domain_info *info = dev_iommu_priv_get(dev); + struct intel_iommu *iommu = info->iommu; + unsigned long flags; + + iommu_disable_dev_iotlb(info); + if (!dev_is_real_dma_subdevice(dev)) { + if (sm_supported(iommu)) + intel_pasid_tear_down_entry(iommu, dev, + PASID_RID2PASID, false); + else + domain_context_clear(info); + } + + if (!info->domain) + return; + + spin_lock_irqsave(&info->domain->lock, flags); + list_del(&info->link); + spin_unlock_irqrestore(&info->domain->lock, flags); + + domain_detach_iommu(info->domain, iommu); + info->domain = NULL; +} + static int md_domain_init(struct dmar_domain *domain, int guest_width) { int adjust_width; @@ -4232,7 +4264,7 @@ static int intel_iommu_attach_device(struct iommu_domain *domain, struct device_domain_info *info = dev_iommu_priv_get(dev); if (info->domain) - dmar_remove_one_dev_info(dev); + device_block_translation(dev); } ret = prepare_domain_attach_device(domain, dev);