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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k131-20020a633d89000000b0046ed15af9d1si4849443pga.213.2022.11.12.06.11.57; Sat, 12 Nov 2022 06:12:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@aurel32.net header.s=202004.hall header.b=LDrjdSPF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234850AbiKLOLn (ORCPT + 99 others); Sat, 12 Nov 2022 09:11:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231146AbiKLOLl (ORCPT ); Sat, 12 Nov 2022 09:11:41 -0500 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0208F5A2; Sat, 12 Nov 2022 06:11:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=SjEaXE1aM3sAT5W9UJJ2Ph7aLEZJwNJ56ePTNEKDEp4=; b=LDrjdSPFEziZCwN4Y9LHueqhRs FzyEjkUZdrZu+mHBxq9WPyaMizEA+alzGmOtxFuC86ZMHA5kclDcKJhNJVvdCaYmvqpbUV9tHeHX5 lMzg+k1ZKd4XeIZAptDlXfPVp0mrimCTomp6+DeBUsKRsdgGAHtDqhnsz4UNWsxZuiemd7frHLLZA c9AwiZwN9s5rHhvtC5eqBhSqpS8ii1vUtxBeGoW8dRbjPcDWIrJSCbRzspzPzuWfX/QynQ4YBuD5S +Ggb4h6Xl7WFWRJljFzqoeF/wvwEFCSOSdy7choARmkM3+zoigTzJlciM8P2W2FTHN64+PCERRvG8 k2zghOcQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1otrE5-00AbR1-JP; Sat, 12 Nov 2022 15:11:17 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1otrE4-00FxDo-2c; Sat, 12 Nov 2022 15:11:16 +0100 From: Aurelien Jarno To: Olivia Mackall , Herbert Xu , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Lin Jinhan Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR CORE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list), Aurelien Jarno Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x Date: Sat, 12 Nov 2022 15:10:59 +0100 Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> References: <20221112141059.3802506-1-aurelien@aurel32.net> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749299855234329572?= X-GMAIL-MSGID: =?utf-8?q?1749299855234329572?= Enable the just added Rockchip RNG driver for RK356x SoCs. Signed-off-by: Aurelien Jarno --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 164708f1eb67..4be94ff45180 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -1770,6 +1770,15 @@ usb2phy1_otg: otg-port { }; }; + rng: rng@fe388000 { + compatible = "rockchip,rk3568-rng"; + reg = <0x0 0xfe388000 0x0 0x4000>; + clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; + clock-names = "trng_clk", "trng_hclk"; + resets = <&cru SRST_TRNG_NS>; + reset-names = "reset"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>;