diff mbox series

[v2,07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node

Message ID	20221111032515.3460-8-quic_bjorande@quicinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Bjorn Andersson <quic_bjorande@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Sibi Sankar <quic_sibis@quicinc.com> CC: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Georgi Djakov <djakov@kernel.org>, Rob Herring <robh+dt@kernel.org>, Mike Tipton <quic_mdtipton@quicinc.com>, Johan Hovold <johan+linaro@kernel.org>, <linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node Date: Thu, 10 Nov 2022 19:25:12 -0800 Message-ID: <20221111032515.3460-8-quic_bjorande@quicinc.com> In-Reply-To: <20221111032515.3460-1-quic_bjorande@quicinc.com> References: <20221111032515.3460-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk
Series	interconnect: osm-l3: SC8280XP L3 and DDR scaling \| [v2,00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling [v2,01/10] interconnect: qcom: osm-l3: Use platform-independent node ids [v2,02/10] interconnect: qcom: osm-l3: Squash common descriptors [v2,03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support [v2,04/10] interconnect: qcom: osm-l3: Simplify osm_l3_set() [v2,05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles [v2,06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3 [v2,07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node [v2,08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling [v2,09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances [v2,10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances

Commit Message

Bjorn Andersson Nov. 11, 2022, 3:25 a.m. UTC

  Add a device node for the EPSS L3 frequency domain.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Sibi Sankar Nov. 11, 2022, 10:33 a.m. UTC | #1

On 11/11/22 08:55, Bjorn Andersson wrote:
> Add a device node for the EPSS L3 frequency domain.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 6bc12e507d21..0e80cdcf6bcf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1782,6 +1782,16 @@
>   			};
>   		};
>   
> +		epss_l3: interconnect@18590000 {
> +			compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
> +			reg = <0 0x18590000 0 0x1000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +
> +			#interconnect-cells = <1>;
> +		};
> +
>   		cpufreq_hw: cpufreq@18591000 {
>   			compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
>   			reg = <0 0x18591000 0 0x1000>,

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 6bc12e507d21..0e80cdcf6bcf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1782,6 +1782,16 @@ 
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,