diff mbox series

[v2,10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances

Message ID	20221111032515.3460-11-quic_bjorande@quicinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Bjorn Andersson <quic_bjorande@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Rob Herring <robh+dt@kernel.org>, Sibi Sankar <quic_sibis@quicinc.com> CC: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Georgi Djakov <djakov@kernel.org>, Mike Tipton <quic_mdtipton@quicinc.com>, Johan Hovold <johan+linaro@kernel.org>, <linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances Date: Thu, 10 Nov 2022 19:25:15 -0800 Message-ID: <20221111032515.3460-11-quic_bjorande@quicinc.com> In-Reply-To: <20221111032515.3460-1-quic_bjorande@quicinc.com> References: <20221111032515.3460-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk
Series	interconnect: osm-l3: SC8280XP L3 and DDR scaling \| [v2,00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling [v2,01/10] interconnect: qcom: osm-l3: Use platform-independent node ids [v2,02/10] interconnect: qcom: osm-l3: Squash common descriptors [v2,03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support [v2,04/10] interconnect: qcom: osm-l3: Simplify osm_l3_set() [v2,05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles [v2,06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3 [v2,07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node [v2,08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling [v2,09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances [v2,10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances

Commit Message

Bjorn Andersson Nov. 11, 2022, 3:25 a.m. UTC

  Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
DDR, with bandwidth values based on the downstream DeviceTree.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- Added "cpu" to compatible for the CPU-subsystem bwmon instance

 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 91 ++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

Comments

Sibi Sankar Nov. 11, 2022, 11:03 a.m. UTC | #1

On 11/11/22 08:55, Bjorn Andersson wrote:
> Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
> DDR, with bandwidth values based on the downstream DeviceTree.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - Added "cpu" to compatible for the CPU-subsystem bwmon instance
> 
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 91 ++++++++++++++++++++++++++
>   1 file changed, 91 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 2ac8f5204905..62e9dd8a2f07 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1287,6 +1287,97 @@
>   			};
>   		};
>   
> +		pmu@9091000 {
> +			compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> +			reg = <0 0x9091000 0 0x1000>;
> +
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
> +
> +			operating-points-v2 = <&llcc_bwmon_opp_table>;
> +
> +			llcc_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <762000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <1720000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <2086000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <2597000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <2929000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <3879000>;
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <5161000>;
> +				};
> +				opp-7 {
> +					opp-peak-kBps = <5931000>;
> +				};
> +				opp-8 {
> +					opp-peak-kBps = <6515000>;
> +				};
> +				opp-9 {
> +					opp-peak-kBps = <7980000>;
> +				};
> +				opp-10 {
> +					opp-peak-kBps = <8136000>;
> +				};
> +				opp-11 {
> +					opp-peak-kBps = <10437000>;
> +				};
> +				opp-12 {
> +					opp-peak-kBps = <12191000>;
> +				};
> +			};
> +		};
> +
> +		pmu@90b6400 {
> +			compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
> +			reg = <0 0x090b6400 0 0x600>;
> +
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +			operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> +			cpu_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <2288000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <4577000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <7110000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <9155000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <12298000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <14236000>;
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <15258001>;
> +				};
> +			};
> +		};
> +
>   		system-cache-controller@9200000 {
>   			compatible = "qcom,sc8280xp-llcc";
>   			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 2ac8f5204905..62e9dd8a2f07 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1287,6 +1287,97 @@ 
 			};
 		};
 
+		pmu@9091000 {
+			compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0 0x9091000 0 0x1000>;
+
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <762000>;
+				};
+				opp-1 {
+					opp-peak-kBps = <1720000>;
+				};
+				opp-2 {
+					opp-peak-kBps = <2086000>;
+				};
+				opp-3 {
+					opp-peak-kBps = <2597000>;
+				};
+				opp-4 {
+					opp-peak-kBps = <2929000>;
+				};
+				opp-5 {
+					opp-peak-kBps = <3879000>;
+				};
+				opp-6 {
+					opp-peak-kBps = <5161000>;
+				};
+				opp-7 {
+					opp-peak-kBps = <5931000>;
+				};
+				opp-8 {
+					opp-peak-kBps = <6515000>;
+				};
+				opp-9 {
+					opp-peak-kBps = <7980000>;
+				};
+				opp-10 {
+					opp-peak-kBps = <8136000>;
+				};
+				opp-11 {
+					opp-peak-kBps = <10437000>;
+				};
+				opp-12 {
+					opp-peak-kBps = <12191000>;
+				};
+			};
+		};
+
+		pmu@90b6400 {
+			compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
+			reg = <0 0x090b6400 0 0x600>;
+
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <2288000>;
+				};
+				opp-1 {
+					opp-peak-kBps = <4577000>;
+				};
+				opp-2 {
+					opp-peak-kBps = <7110000>;
+				};
+				opp-3 {
+					opp-peak-kBps = <9155000>;
+				};
+				opp-4 {
+					opp-peak-kBps = <12298000>;
+				};
+				opp-5 {
+					opp-peak-kBps = <14236000>;
+				};
+				opp-6 {
+					opp-peak-kBps = <15258001>;
+				};
+			};
+		};
+
 		system-cache-controller@9200000 {
 			compatible = "qcom,sc8280xp-llcc";
 			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;