From patchwork Thu Nov 10 17:58:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 18259 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp294454wru; Thu, 10 Nov 2022 10:08:02 -0800 (PST) X-Google-Smtp-Source: AMsMyM7H1YRba5VQAwKkrei8RMYbPVNQKtQd71AB47Y8C0OWGmGF7pAHlN56+JuQ731zOolWSVih X-Received: by 2002:a05:6402:cb7:b0:461:17e9:4ea3 with SMTP id cn23-20020a0564020cb700b0046117e94ea3mr2901649edb.49.1668103681844; Thu, 10 Nov 2022 10:08:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1668103681; cv=pass; d=google.com; s=arc-20160816; b=UPRypo0FRFqGb8EQEcHRW1dKd1Oh4S2TahKmOeMwVloN8eE+KukWjEszcX1VHRcVq+ mdLf+YugV29eFrCeoB1cUqHUS8EWvtUsDNSPB629Aym3wjV+ZonVetrA0UsebQHzt2u9 QmWwPd3KjduqkcK3pDkHfOHDMiqIW1tJBs7HWi5ZWhj3OSGS6XGKgAOEBzfwGl8BazNo qtRkjOHnkopKXw0ApINz1U+bbCl/0lxEgJBnM1doYvPumOP7mV1K4yvpmKZucGz4nPov ftryy/av9ZHiv3B6OR2s5mWwFjFsl1TT+8zOA70D+KXe1i9lq8Ou9JCc7JjisAinuiKh /a4Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ez8uo72CVG7SAWYMv0jK3unq2c24Hz4ZH5D21jPoAHg=; b=jrDmDsbz0EDKECoqnUpNRmvmlUppL499pn4JIlADq+vqvAjk894FOQEUl6CBHoIFzy EOjZotx+uzkVzal3qhBghjG28eKkVe33Ut8D9rR1bzmdg6uH4NJonfUnokNjyvpkSwy7 nccUw886FSpC3qAJkcJKYlLhzDR10p/gkd9sugp7N/K/qCLIVrpqBfXKW8cGKGfniBva iK4V02pT1pCm3pPdAA8CrnCczSMjTzkKw1jtOHpvXG6VQMz9eSXH2pQ4IrH7ENJJ0gkC Yd2rldyGxQRpdVamhEWV1mblA84nYCLyr9bElT86juEsQtzBVDjTTOpulStd8GNELXLY NUXw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=3r4LC6K1; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sb6-20020a1709076d8600b007ae54733c69si17060437ejc.542.2022.11.10.10.07.07; Thu, 10 Nov 2022 10:08:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=3r4LC6K1; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231529AbiKJR7b (ORCPT + 99 others); Thu, 10 Nov 2022 12:59:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231586AbiKJR7W (ORCPT ); Thu, 10 Nov 2022 12:59:22 -0500 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2049.outbound.protection.outlook.com [40.107.92.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBFF64730C; Thu, 10 Nov 2022 09:59:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nNjVTPrZQ12fLE3aOrDRFAchMpnRqXMrrOKGjFlmF2d59XJQbA8dalOnc7bj+W43wtFzaX0Fo0omRscuILdTp1j8ASRlwj4B7yo706qI9YvSk9Bzuh3oNh2AI/zd6HfHGDYzmSWj4W2gr4KIlwstoJtFkdV4OKICUf5JF86/ygJLxjJN8Jfb6CTZESHT8Rb8wUSKEn1WoxbI85B6hnqzxlcx/b5LYlWsYLpk4Tb2w7OWWA2z/cbkldTVOSM1qWBHOzeB0qso10hFBaPFsMSV9HgbDwa7z9jP/kopL0UFQRlQV/4oNUSj2+y7A9o7rDrurIsIlF+7vO30Jk3/ZG/e2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Ez8uo72CVG7SAWYMv0jK3unq2c24Hz4ZH5D21jPoAHg=; b=XUwaktPMakn8cZ/UJWG85HrkGPnkUI4XZuHHvVfzT9iQdrShNab3/+fwJ2Gc8QE4ESwum//IyCBa8k5hNDpUfvBEhSM0plcFZcHvibZG1skGhOf6QTTZN7k9BvvmD1+f5Fr9p+k4Hbl8g00qEk3qauYxSteyADmU8ymcvlSEBHTyHSm0AGi8okQNYphXaAbY3FyAFMLWfFTJTh2BU+fXTQGoXVjgIWAWJwQKpu1KoDWABB0NGVuQ4RoZ22QoKp1UojZCAbtLUOmlii7x+wsXHK7TRjbxldiEZGtywcb2bG2D8lrzHBB+xvRJtXKrNWDzIgFoJe+HCAecB3CTI+KLmA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ez8uo72CVG7SAWYMv0jK3unq2c24Hz4ZH5D21jPoAHg=; b=3r4LC6K16LCRZmCz5qheMzMvMgN07LtSNm+cKBngrZ0u+HgcCiQ5sFc811r4RUpq68J4aXxrLAZNPVu2Ko+MAFkZ/cfjhf49/h8uWyKxKnkz3ISRTJ94dRr7VqvcZK1kIdvwzNmPeIWQAfhaA8LZdUNEZ7HeIQE6lyk3I1T5/kI= Received: from BN9PR03CA0396.namprd03.prod.outlook.com (2603:10b6:408:111::11) by MN2PR12MB4301.namprd12.prod.outlook.com (2603:10b6:208:1d4::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27; Thu, 10 Nov 2022 17:59:16 +0000 Received: from BN8NAM11FT051.eop-nam11.prod.protection.outlook.com (2603:10b6:408:111:cafe::5f) by BN9PR03CA0396.outlook.office365.com (2603:10b6:408:111::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27 via Frontend Transport; Thu, 10 Nov 2022 17:59:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT051.mail.protection.outlook.com (10.13.177.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5813.12 via Frontend Transport; Thu, 10 Nov 2022 17:59:16 +0000 Received: from pyuan-Cloudripper.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Thu, 10 Nov 2022 11:59:12 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v4 1/9] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Date: Fri, 11 Nov 2022 01:58:39 +0800 Message-ID: <20221110175847.3098728-2-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221110175847.3098728-1-Perry.Yuan@amd.com> References: <20221110175847.3098728-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT051:EE_|MN2PR12MB4301:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f0bf5b0-ce77-44cd-82bf-08dac3454873 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Y1lxgkeVpsMIRNERdLK8NOBHvrhZLwMMp4h6wnj0fmi4AyRqaAAnS6vepKxXc6FRnPqn4NGKCzDWE/Otjw1IsPIbwkBK1Nvo2m4S2LZ97Kf75Wwsx9llR7Lone6epqZrsR2B8E1OR2jTRcLl3EvPhPKiCDEhNuqge1KHrBxGy21EIPJY7zsyofO7xd3Lzkx6vfuA81mwWRsGN5J9gyJ0j4PGo/HuQgXR75x0ImtEi5NFb2/brNI1+BjS4mqoRXwM8LoUb96pGcBskIe3iO1Y7a7Xyt101jBCZ+IXeXNgOPke7BL4viaqtDOU5OJtPF21KFsGbkB02t2rzr3gBcTcI0VdXcHgphclOPuzG69Ky8B29L6jdqk+wj0kwHyb4foxsn4Ubn695NbVhrXmmLgx4PRokaH4Y223D+3REY48eX9HhglO0E+R5DVeavVRJvcJbH+3xlMxsVBblQ17Nj2nv+Rat2nRxifan3O1e05qbblVXZbuSCyOMQ/8BJnrZjdoquxI1Sm8/nUQ7m95Ps9L4rIORn2o2NT2g0fvQNzyJu5aaLYShYzO0AFcKzzChOOS+8Dx5xQ0314QzzNIt+XFcOBm1WwvcTyZv5ckGENKcBZOv4lT7uK1GYjF6XEdcKwGHHDDAceFcjh1PDDCmFNvR55Q5UPFc9tM3OQ/GY6su+TXsQfiN19inBNmDx7oHfkVblhSGXpdEpE4T4eHHWTxZ9StP4Q0eTMd2E3gCS2jq62RBoEmkiYh31WbidgbcTjCgS5JJ8O9XDVBfc9uKPBOeLFqw4tfWv1GUJwqMpnX8PTBlXC1St1kbyncw5V6grnW X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(478600001)(2906002)(2616005)(1076003)(36860700001)(16526019)(36756003)(186003)(336012)(6666004)(83380400001)(81166007)(82310400005)(356005)(47076005)(82740400003)(26005)(4326008)(40460700003)(7696005)(426003)(8676002)(40480700001)(70206006)(70586007)(8936002)(86362001)(316002)(5660300002)(41300700001)(54906003)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 17:59:16.1567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f0bf5b0-ce77-44cd-82bf-08dac3454873 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4301 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749133486299621247?= X-GMAIL-MSGID: =?utf-8?q?1749133486299621247?= Add support for setting and querying EPP preferences to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values In order to get EPP worked, cppc_get_epp_caps() will query EPP preference value and cppc_set_epp_perf() will set EPP new value. Before the EPP works, pstate driver will use cppc_set_auto_epp() to enable EPP function from firmware firstly. Signed-off-by: Perry Yuan --- drivers/acpi/cppc_acpi.c | 114 +++++++++++++++++++++++++++++++++++++-- include/acpi/cppc_acpi.h | 12 +++++ 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 093675b1a1ff..37fa75f25f62 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1093,6 +1093,9 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *reg; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@ -1102,10 +1105,6 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) reg = &cpc_desc->cpc_regs[reg_idx]; if (CPC_IN_PCC(reg)) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = 0; - if (pcc_ss_id < 0) return -EIO; @@ -1125,7 +1124,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) cpc_read(cpunum, reg, perf); - return 0; + return ret; } /** @@ -1365,6 +1364,111 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_get_epp_caps - Get the energy preference register value. + * @cpunum: CPU from which to get epp preference level. + * @perf_caps: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *energy_perf_reg; + u64 energy_perf; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (!CPC_SUPPORTED(energy_perf_reg)) + pr_warn_once("energy perf reg update is unsupported!\n"); + + if (CPC_IN_PCC(energy_perf_reg)) { + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0; + + if (pcc_ss_id < 0) + return -ENODEV; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { + cpc_read(cpunum, energy_perf_reg, &energy_perf); + perf_caps->energy_perf = energy_perf; + } else { + ret = -EIO; + } + + up_write(&pcc_ss_data->pcc_lock); + + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_epp_caps); + +/* + * Set Energy Performance Preference Register value through + * Performance Controls Interface + */ +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *epp_set_reg; + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + if (CPC_SUPPORTED(auto_sel_reg)) { + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + if (CPC_SUPPORTED(epp_set_reg)) { + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + } + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } else { + ret = -ENOTSUPP; + pr_debug("_CPC in PCC is not supported\n"); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c5614444031f..a93393b05171 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -108,12 +108,14 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; + u32 energy_perf; }; struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -149,6 +151,8 @@ extern bool cpc_ffh_supported(void); extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -202,6 +206,14 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { return -ENOTSUPP; } +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, boot enable) +{ + return -ENOTSUPP; +} +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + return -ENOTSUPP; +} #endif /* !CONFIG_ACPI_CPPC_LIB */ #endif /* _CPPC_ACPI_H*/