[2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Commit Message
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
create mode 100644 include/dt-bindings/mmc/meson-gx-mmc.h
Comments
Hi Vyacheslav,
On Thu, Nov 10, 2022 at 4:02 PM Vyacheslav Bocharov <adeep@lexina.in> wrote:
[...]
> +/*
> + * Cfg_rx_phase: RX clock phase
> + * bits: 9:8 R/W
Generally register values should not be part of the dt-bindings.
If we need to make the phases configurable through device-tree then I
suggest using the human readable values (0, 90, 180, 270) instead of
these register bits.
That said, if for whatever reason we need to have #defines for this
then they should be added with the dt-bindings patch (and also carry
the dt-bindings subject prefix) instead of a separate patch.
Best regards,
Martin
new file mode 100644
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2022 JetHome, Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
+#define _DT_BINDINGS_MESON_GX_MMC_H
+
+/*
+ * Cfg_rx_phase: RX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 0
+ *
+ * Cfg_tx_phase: TX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * Cfg_co_phase: Core clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
+ */
+
+#define CLK_PHASE_0 0
+#define CLK_PHASE_90 1
+#define CLK_PHASE_180 2
+#define CLK_PHASE_270 3
+
+
+#endif