From patchwork Thu Nov 10 15:00:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viacheslav X-Patchwork-Id: 18157 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp203265wru; Thu, 10 Nov 2022 07:12:27 -0800 (PST) X-Google-Smtp-Source: AMsMyM6iFgT8Selg8jv+j44ZqfeZybZim/j6cggKv+WVIVgn0yBPDU1W0fstZ+MUTZUr79aQgci1 X-Received: by 2002:a17:906:454c:b0:7a2:b352:a0d3 with SMTP id s12-20020a170906454c00b007a2b352a0d3mr2927308ejq.399.1668093147083; Thu, 10 Nov 2022 07:12:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668093147; cv=none; d=google.com; s=arc-20160816; b=lqPTGxYZLL3KqzeT91mKpCtdW1SVUuA6hpiOytFBA9HV1MFtSdt0FgN5ox12YXmFvq yArsnnX9MaKupVs+BU8/lNaxaT6ITSO6RF6hVzeQ1svPDyCrzvMetsMvjdL/i93j675L crKHfmn6dnR8oAaO5smdvwKdCc8p37hvi3AYboGivxiSPiFjfcwosnoBDpDzEOFCl2DH /8gIQhPdn6wA9KoCE/OxjtAqv608lXgmDgU97CQWBMGDuIMhSkWZQbdepJDzG+TYY5SH DzFBj+LeD/9c/FR8EuPICM+gxZqeii9I7XkZldZg23dSszOAesW5AeiJz0bdLnkQpnrK izjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZftRKqAeH5kEZiPRpVJLIZ6Af/f8rleyvcwfQTNcp7I=; b=eA3ZMaS5KL7gdh4Stts/Z4m1mnvb0sP8hd7VSFk7gwuhe+ulnLMSCKU9KEhRNCPCPd Fxy0U/1vNNVo0fJQTDedJX38RnSebwWhfbXaDUDC7CppJ1QAjHioN7zijghvyX7VfU58 g11xAQPErcH8JDO+XWu7OcfC4cmHpNg3d7SElehyVzaZUErjYLlcN/8sdzT8ce89n50H AA9yg8Sv2FVaaw4o9ok7KMXJLWTUQjc/UPUaayPIYj/X4UQvwnwGbUDyO8U1LGnyOEY5 pLV2z/fA/EVZBOStk6GhaRUeSd+DLR9iESvfojSO1pnE/kEASS3mjljWXIclMvQZEeRb kIQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lexina.in header.s=dkim header.b=iBqP2MLx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=lexina.in Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d21-20020a056402517500b004614db9789asi14563177ede.127.2022.11.10.07.12.01; Thu, 10 Nov 2022 07:12:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@lexina.in header.s=dkim header.b=iBqP2MLx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=lexina.in Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231298AbiKJPI6 (ORCPT + 99 others); Thu, 10 Nov 2022 10:08:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbiKJPIm (ORCPT ); Thu, 10 Nov 2022 10:08:42 -0500 Received: from mx.msync.work (mx.msync.work [185.250.0.168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CF9F23149; Thu, 10 Nov 2022 07:08:38 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 41848123166; Thu, 10 Nov 2022 15:01:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lexina.in; s=dkim; t=1668092467; h=from:subject:date:message-id:to:mime-version: content-transfer-encoding:in-reply-to:references; bh=ZftRKqAeH5kEZiPRpVJLIZ6Af/f8rleyvcwfQTNcp7I=; b=iBqP2MLxyMk8eCbFAdaeuExuIOALRKLLZSDpRtsRyVV6+urGSwF4pvBL4sqhn2FKo5pIcG 9RukbBC9aFvVOD0PBymrIR8Yl5tG0APoGBPTtAZqYX0llwiGPdtkso+w3R5S5vx36iaKTd G1Oib53dVrYaq5ywCwggn5htG64J3Ifgku9cs9CZMYzXxYCfx2hbCdkfS9/Ne9qjRnm3jH KdJlzMNyepdljw4YnL0PXZjRxXWWscIGgIRPSVpCt0bIdzVhi1UsGE4yQbBKD9IMwzGBAL IcWrMtnp4/4GuFYrvG4QUS5q693UmEdH1f4hFdV4N3nk0etdMhYv0dF8Ku3hOw== From: Vyacheslav Bocharov To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data Date: Thu, 10 Nov 2022 18:00:32 +0300 Message-Id: <20221110150035.2824580-2-adeep@lexina.in> In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in> References: <20221110150035.2824580-1-adeep@lexina.in> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749122439687505528?= X-GMAIL-MSGID: =?utf-8?q?1749122439687505528?= The mmc driver has the same phase values for all meson platforms. However, some platforms (and even some boards) require different values. This patch transfers the values from the set in the code to the variables in the device-tree file. Signed-off-by: Vyacheslav Bocharov diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index df05e60bed9a..c0f32054e472 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -27,6 +27,7 @@ #include #include #include +#include #define DRIVER_NAME "meson-gx-mmc" @@ -36,8 +37,6 @@ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) -#define CLK_PHASE_0 0 -#define CLK_PHASE_180 2 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) #define CLK_V2_ALWAYS_ON BIT(24) @@ -428,13 +427,22 @@ static int meson_mmc_clk_init(struct meson_host *host) const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; const char *clk_parent[1]; u32 clk_reg; + u32 phase[3]; // + + if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev, + "amlogic,mmc-phase", phase, 3) < 0)) { + dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n"); + phase[0] = CLK_PHASE_180; + phase[1] = CLK_PHASE_0; + phase[2] = CLK_PHASE_0; + } /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = CLK_ALWAYS_ON(host); clk_reg |= CLK_DIV_MASK; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]); clk_reg |= CLK_IRQ_SDIO_SLEEP(host); writel(clk_reg, host->regs + SD_EMMC_CLOCK);