[4/9] arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD
Commit Message
Enable the NVMe SSD connected to PCIe2.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++
1 file changed, 63 insertions(+)
Comments
On 10/11/2022 11:35, Johan Hovold wrote:
> Enable the NVMe SSD connected to PCIe2.
>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 0801bd8c44fb..fd2bdfd1126b 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -50,6 +50,20 @@ vreg_edp_bl: regulator-edp-bl {
> regulator-boot-on;
> };
>
> + vreg_nvme: regulator-nvme {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VCC3_SSD";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&nvme_reg_en>;
> + };
> +
> vreg_misc_3p3: regulator-misc-3p3 {
> compatible = "regulator-fixed";
>
> @@ -178,6 +192,25 @@ vreg_l9d: ldo9 {
> };
> };
>
> +&pcie2a {
> + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
> +
> + vddpe-3v3-supply = <&vreg_nvme>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie2a_default>;
> +
> + status = "okay";
> +};
> +
> +&pcie2a_phy {
> + vdda-phy-supply = <&vreg_l6d>;
> + vdda-pll-supply = <&vreg_l4d>;
> +
> + status = "okay";
> +};
> +
> &pmc8280c_lpg {
> status = "okay";
> };
> @@ -393,6 +426,36 @@ reset-pins {
> };
> };
>
> + nvme_reg_en: nvme-reg-en-state {
> + pins = "gpio135";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + pcie2a_default: pcie2a-default-state {
Aren't they going to be identical for all boards anyway? Maybe there
could be some commonization..
Konrad
> + clkreq-n-pins {
> + pins = "gpio142";
> + function = "pcie2a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio143";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + wake-n-pins {
> + pins = "gpio145";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> qup0_i2c4_default: qup0-i2c4-default-state {
> pins = "gpio171", "gpio172";
> function = "qup4";
On Thu, Nov 10, 2022 at 12:06:45PM +0100, Konrad Dybcio wrote:
> On 10/11/2022 11:35, Johan Hovold wrote:
> > Enable the NVMe SSD connected to PCIe2.
> >
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---
> > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++
> > 1 file changed, 63 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > + pcie2a_default: pcie2a-default-state {
>
> Aren't they going to be identical for all boards anyway? Maybe there
> could be some commonization..
We had that discussion and decided that keeping the pinconfig in the dts
is the right thing to do.
And even if the clkreq pin will be the same for all boards that's not
necessarily the case for the other two.
> > + clkreq-n-pins {
> > + pins = "gpio142";
> > + function = "pcie2a_clkreq";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + perst-n-pins {
> > + pins = "gpio143";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + wake-n-pins {
> > + pins = "gpio145";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > qup0_i2c4_default: qup0-i2c4-default-state {
> > pins = "gpio171", "gpio172";
> > function = "qup4";
Johan
On 11/11/2022 17:22, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 12:06:45PM +0100, Konrad Dybcio wrote:
>> On 10/11/2022 11:35, Johan Hovold wrote:
>>> Enable the NVMe SSD connected to PCIe2.
>>>
>>> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
>>> ---
>>> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++
>>> 1 file changed, 63 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>>> + pcie2a_default: pcie2a-default-state {
>> Aren't they going to be identical for all boards anyway? Maybe there
>> could be some commonization..
> We had that discussion and decided that keeping the pinconfig in the dts
> is the right thing to do.
>
> And even if the clkreq pin will be the same for all boards that's not
> necessarily the case for the other two.
Okay then. I simply keep forgetting which pins we concluded go where..
Konrad
>
>>> + clkreq-n-pins {
>>> + pins = "gpio142";
>>> + function = "pcie2a_clkreq";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> +
>>> + perst-n-pins {
>>> + pins = "gpio143";
>>> + function = "gpio";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> +
>>> + wake-n-pins {
>>> + pins = "gpio145";
>>> + function = "gpio";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> + };
>>> +
>>> qup0_i2c4_default: qup0-i2c4-default-state {
>>> pins = "gpio171", "gpio172";
>>> function = "qup4";
> Johan
@@ -50,6 +50,20 @@ vreg_edp_bl: regulator-edp-bl {
regulator-boot-on;
};
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3_SSD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_reg_en>;
+ };
+
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";
@@ -178,6 +192,25 @@ vreg_l9d: ldo9 {
};
};
+&pcie2a {
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2a_default>;
+
+ status = "okay";
+};
+
+&pcie2a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
@@ -393,6 +426,36 @@ reset-pins {
};
};
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio135";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie2a_default: pcie2a-default-state {
+ clkreq-n-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";