From patchwork Thu Nov 10 06:37:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 17967 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp759864wru; Wed, 9 Nov 2022 22:39:46 -0800 (PST) X-Google-Smtp-Source: AMsMyM5Gb3mnHN/1T6CwnR06SVNcI7DHV5tBAo4Y7lEA8PzNZe9m6bjaCbwbH025nq7p7fhMozGl X-Received: by 2002:a17:90b:1948:b0:214:1ae7:a511 with SMTP id nk8-20020a17090b194800b002141ae7a511mr46307472pjb.89.1668062385721; Wed, 09 Nov 2022 22:39:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668062385; cv=none; d=google.com; s=arc-20160816; b=xzK82Iq3p3jA5fUTrzx1zdRHKIdmGX7rHCnna4AHnqLwZjeJmb74br8aUv+0fsaYzr MTq9CuwqsI9ABNPSTzRumlEsYGUDIaebuyAtKfzpT28ivW1I44n9O3MHO/9GO1Ifu+Hv zhEim175rpZsnrrF6MC6woUuK0OJGICdjJJQsUJNidYqAq6I1Pn8OA2LMBzKp6QJRU37 sFmpG392MiLoDXxA6tpgCETbeSzUugLYnS6ryr4ezYir0YFIfRKmpDlgy7NhjAM//MkS +snw1f9ptGc4H2onhy0LAgvVzkMxwQ5nyOxGupVqmYu1Ysf+RHOGhHpRXG4Oo6Fi83c2 ungg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=IYNsu3+YhsLdxa/TdV8zExfZobnqiPHL5UL2NPZZAqU=; b=IRoaBsTP01SCohoBMt1rgsrklAFKLqQOD/eSMrsTHWWj6YWTFcMIcoWwVDqWZiTroK lJxSqgroT/5T1QQPaReeAPtHPOBO4LBW+GwfxfQTR5KU3zGzV+L0FbMtCh6R6CHrzvRx RuE++9aWwiGcJ3zNB5YX8LujJRJx15ydXvJiqHSatwhCaZppSJDwfiOGBHvYRC4sIuGk r1IRMOqgifOJ+YQ/sNyKA97WBAfkCT2Zt7RHL27Tk7uFXgMHFqDIZ487CtWIjGE+kFIL TrDzEt8ix7rxnfqpCGIzDKVtZ1+aTZn6yIUrxZDytc8ImoTgX8d3rk5yUZupD3a7Z021 i0Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=YImq3n3h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v202-20020a6361d3000000b0045abcc62064si17453464pgb.695.2022.11.09.22.39.31; Wed, 09 Nov 2022 22:39:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=YImq3n3h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232471AbiKJGhd (ORCPT + 99 others); Thu, 10 Nov 2022 01:37:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232505AbiKJGh3 (ORCPT ); Thu, 10 Nov 2022 01:37:29 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD9B62CE09; Wed, 9 Nov 2022 22:37:24 -0800 (PST) X-UUID: 84fcb39d4bea492493923d02ce175217-20221110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IYNsu3+YhsLdxa/TdV8zExfZobnqiPHL5UL2NPZZAqU=; b=YImq3n3hByXXLCJE79wAdUBeJXRNslKfuWyZiU0Yhz56pGZfe6ktluQcsUQYJNOZ9JSgY+wq9ErYcvZMLXS09af7XOo2Q0WOpg9re4otSaueCrQibWsK5vKokwS/KSGr0vgOGhke92EuRYeViY4JDKUWxaN/vCZLiogqvAplE8w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:7b107302-070d-47e8-8e77-fe11386b47ab,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:62cd327,CLOUDID:9e12e350-b7af-492d-8b40-b1032f90ce11,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 84fcb39d4bea492493923d02ce175217-20221110 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1855394692; Thu, 10 Nov 2022 14:37:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 10 Nov 2022 14:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 10 Nov 2022 14:37:18 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v4 1/4] arm64: dts: mt8195: Add dp-intf nodes Date: Thu, 10 Nov 2022 14:37:13 +0800 Message-ID: <20221110063716.25677-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221110063716.25677-1-rex-bc.chen@mediatek.com> References: <20221110063716.25677-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749090184177936922?= X-GMAIL-MSGID: =?utf-8?q?1749090184177936922?= Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 nodes. Dp-intf0 is for edptx and dp-intf1 is for dptx. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2edfc21ece56..c380738d10cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2094,6 +2094,17 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; + dp_intf0: dp-intf@1c015000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c015000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + mutex: mutex@1c016000 { compatible = "mediatek,mt8195-disp-mutex"; reg = <0 0x1c016000 0 0x1000>; @@ -2182,5 +2193,17 @@ clock-names = "apb", "smi", "gals"; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; }; };