diff mbox series

[v3,9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support

Message ID 20221109104059.766720-10-rrichter@amd.com
State New
Headers
Series cxl: Add support for Restricted CXL hosts (RCD mode) |

Commit Message

Robert Richter Nov. 9, 2022, 10:40 a.m. UTC 
  From: Terry Bowman <terry.bowman@amd.com>

ACPI includes a CXL _OSC support procedure to communicate the available
CXL support to FW. The CXL support _OSC includes a field to indicate
CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access
to RCD and RCH Port registers.[1] FW can potentially change it's operation
depending on the _OSC support setting reported by the OS.

The ACPI driver does not currently set the ACPI _OSC support to indicate
CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1.

[1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field'

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/acpi/pci_root.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Rafael J. Wysocki Nov. 9, 2022, 12:22 p.m. UTC | #1 
On Wed, Nov 9, 2022 at 11:41 AM Robert Richter <rrichter@amd.com> wrote:
>
> From: Terry Bowman <terry.bowman@amd.com>
>
> ACPI includes a CXL _OSC support procedure to communicate the available
> CXL support to FW. The CXL support _OSC includes a field to indicate
> CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access
> to RCD and RCH Port registers.[1] FW can potentially change it's operation
> depending on the _OSC support setting reported by the OS.
>
> The ACPI driver does not currently set the ACPI _OSC support to indicate
> CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1.
>
> [1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field'
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

> ---
>  drivers/acpi/pci_root.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index c8385ef54c37..094a59b216ae 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -492,6 +492,7 @@ static u32 calculate_cxl_support(void)
>         u32 support;
>
>         support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> +       support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
>         if (pci_aer_available())
>                 support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
>         if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
> --
> 2.30.2
>
Bjorn Helgaas Nov. 9, 2022, 11:35 p.m. UTC | #2 
On Wed, Nov 09, 2022 at 11:40:59AM +0100, Robert Richter wrote:
> From: Terry Bowman <terry.bowman@amd.com>
> 
> ACPI includes a CXL _OSC support procedure to communicate the available
> CXL support to FW. The CXL support _OSC includes a field to indicate
> CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access
> to RCD and RCH Port registers.[1] FW can potentially change it's operation

s/it's/its/

> depending on the _OSC support setting reported by the OS.
> 
> The ACPI driver does not currently set the ACPI _OSC support to indicate
> CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1.

Eight instances of "support" above seems like it might be more than
necessary.

I don't know the history, but OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT and
OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT seem like sort of weird names
since they don't match the spec at all ("RCD and RCH Port Register
Access Supported" and "CXL VH Register Access Supported").

> [1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field'
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
>  drivers/acpi/pci_root.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index c8385ef54c37..094a59b216ae 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -492,6 +492,7 @@ static u32 calculate_cxl_support(void)
>  	u32 support;
>  
>  	support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> +	support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
>  	if (pci_aer_available())
>  		support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
>  	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
> -- 
> 2.30.2
>
Verma, Vishal L Nov. 10, 2022, 12:51 a.m. UTC | #3 
On Wed, 2022-11-09 at 17:35 -0600, Bjorn Helgaas wrote:
> On Wed, Nov 09, 2022 at 11:40:59AM +0100, Robert Richter wrote:
> > From: Terry Bowman <terry.bowman@amd.com>
> > 
> > ACPI includes a CXL _OSC support procedure to communicate the available
> > CXL support to FW. The CXL support _OSC includes a field to indicate
> > CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access
> > to RCD and RCH Port registers.[1] FW can potentially change it's operation
> 
> s/it's/its/
> 
> > depending on the _OSC support setting reported by the OS.
> > 
> > The ACPI driver does not currently set the ACPI _OSC support to indicate
> > CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1.
> 
> Eight instances of "support" above seems like it might be more than
> necessary.
> 
> I don't know the history, but OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT and
> OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT seem like sort of weird names
> since they don't match the spec at all ("RCD and RCH Port Register
> Access Supported" and "CXL VH Register Access Supported").

Ah the RCH/RCD and VH terminology was only introduced in the CXL-3.0
spec. When the above defines were added, the spec was at 2.0, and it
used the descriptions: "CXL 1.1 Port Register Access supported", and
"CXL 2.0 Port/Device Register Access supported" (Table 217 in 2.0).

> 
> > [1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field'
> > 
> > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > ---
> >  drivers/acpi/pci_root.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> > index c8385ef54c37..094a59b216ae 100644
> > --- a/drivers/acpi/pci_root.c
> > +++ b/drivers/acpi/pci_root.c
> > @@ -492,6 +492,7 @@ static u32 calculate_cxl_support(void)
> >         u32 support;
> >  
> >         support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> > +       support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
> >         if (pci_aer_available())
> >                 support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
> >         if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
> > -- 
> > 2.30.2
> >
Bjorn Helgaas Nov. 10, 2022, 5:10 p.m. UTC | #4 
On Thu, Nov 10, 2022 at 12:51:02AM +0000, Verma, Vishal L wrote:
> On Wed, 2022-11-09 at 17:35 -0600, Bjorn Helgaas wrote:

> > I don't know the history, but OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT and
> > OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT seem like sort of weird names
> > since they don't match the spec at all ("RCD and RCH Port Register
> > Access Supported" and "CXL VH Register Access Supported").
> 
> Ah the RCH/RCD and VH terminology was only introduced in the CXL-3.0
> spec. When the above defines were added, the spec was at 2.0, and it
> used the descriptions: "CXL 1.1 Port Register Access supported", and
> "CXL 2.0 Port/Device Register Access supported" (Table 217 in 2.0).

Haha, that's annoying :)  I didn't dig back through the old versions.
I guess CXL folks can decide whether to keep the old names or update.
Terry Bowman Nov. 10, 2022, 7:43 p.m. UTC | #5 
On 11/9/22 17:35, Bjorn Helgaas wrote:
> On Wed, Nov 09, 2022 at 11:40:59AM +0100, Robert Richter wrote:
>> From: Terry Bowman <terry.bowman@amd.com>
>>
>> ACPI includes a CXL _OSC support procedure to communicate the available
>> CXL support to FW. The CXL support _OSC includes a field to indicate
>> CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access
>> to RCD and RCH Port registers.[1] FW can potentially change it's operation
> 
> s/it's/its/
> 

Ok, will fix.

>> depending on the _OSC support setting reported by the OS.
>>
>> The ACPI driver does not currently set the ACPI _OSC support to indicate
>> CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1.
> 
> Eight instances of "support" above seems like it might be more than
> necessary.
> 
> I don't know the history, but OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT and
> OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT seem like sort of weird names
> since they don't match the spec at all ("RCD and RCH Port Register
> Access Supported" and "CXL VH Register Access Supported").
> 

I'll reword to not excessively reuse 'support'. Thanks for point out.

Regards,
Terry

>> [1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field'
>>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>> Signed-off-by: Robert Richter <rrichter@amd.com>
>> ---
>>  drivers/acpi/pci_root.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
>> index c8385ef54c37..094a59b216ae 100644
>> --- a/drivers/acpi/pci_root.c
>> +++ b/drivers/acpi/pci_root.c
>> @@ -492,6 +492,7 @@ static u32 calculate_cxl_support(void)
>>  	u32 support;
>>  
>>  	support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
>> +	support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
>>  	if (pci_aer_available())
>>  		support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
>>  	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
>> -- 
>> 2.30.2
>>
diff mbox series

Patch

diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index c8385ef54c37..094a59b216ae 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -492,6 +492,7 @@  static u32 calculate_cxl_support(void)
 	u32 support;
 
 	support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
+	support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
 	if (pci_aer_available())
 		support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
 	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))