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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h19-20020a056a00219300b00565de49c23dsi16069208pfi.105.2022.11.08.23.36.06; Tue, 08 Nov 2022 23:36:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=MbVEpgHb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229877AbiKIHft (ORCPT + 99 others); Wed, 9 Nov 2022 02:35:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229797AbiKIHfp (ORCPT ); Wed, 9 Nov 2022 02:35:45 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94A551B1E3; Tue, 8 Nov 2022 23:35:42 -0800 (PST) X-UUID: c2881c867bab4db68f6661cd5398414d-20221109 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=QCk+iUg0ui/F5dLQSuVBDAQrxMc6+fB8oU7bSymkVjE=; b=MbVEpgHbpjGQSPNeo64RfExdXbSP5W3MfJmYHj80Y1O8GP0wvGaFYshVWFLz+anx1l0fWy5I8LneJeq76o11gHFDVbBCSYte1paB43cCKXaJ8sw6rnskfypBMcxdGHXn64IbGlJAzuIkwrCmWvpuFfbCP9A75XzPzj+wHZU5LRA=; X-CID-UNFAMILIAR: 1 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:da47dde7-1fe9-472d-a464-413b6154c00b,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.12,REQID:da47dde7-1fe9-472d-a464-413b6154c00b,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:62cd327,CLOUDID:317e0c91-1a78-4832-bd08-74b1519dcfbf,B ulkID:221109153536R4Z769QE,BulkQuantity:0,Recheck:0,SF:38|28|16|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c2881c867bab4db68f6661cd5398414d-20221109 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 319445144; Wed, 09 Nov 2022 15:35:34 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 9 Nov 2022 15:35:32 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 9 Nov 2022 15:35:31 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH 2/3] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2 Date: Wed, 9 Nov 2022 15:35:28 +0800 Message-ID: <20221109073529.26765-2-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221109073529.26765-1-yunfei.dong@mediatek.com> References: <20221109073529.26765-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749003146056715062?= X-GMAIL-MSGID: =?utf-8?q?1749003146056715062?= Need to add racing control register base in device node for mt8195 support inner racing mode. Changing the max reg value from 1 to 2. Signed-off-by: Yunfei Dong --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 794012853834..1697feb1f854 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -61,7 +61,7 @@ properties: - mediatek,mt8195-vcodec-dec reg: - maxItems: 1 + maxItems: 2 iommus: minItems: 1