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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ee15-20020a056402290f00b004593bcff7e5si12000066edb.475.2022.11.08.06.49.28; Tue, 08 Nov 2022 06:49:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=iJTRDHke; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234704AbiKHOpg (ORCPT + 99 others); Tue, 8 Nov 2022 09:45:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232940AbiKHOoc (ORCPT ); Tue, 8 Nov 2022 09:44:32 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D77F621A6; Tue, 8 Nov 2022 06:44:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667918671; x=1699454671; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mk4FwTKpXPEVthCrmeXfry31BmjDVomdGZScwkkQgyQ=; b=iJTRDHkeMqgn03Vc6Dlg6jFdOiOwU1+zrhyZrnw7JA6dS0GG6pGK9qpn plaC7lZkBe66i9F7pWNmUnUybiuKQUxH2luB4St8lyNqBWoi13WKElsKK dT1H1zlkdczf1XCtEZGWYb3hiQ6mX4U9TL/b/4PYuDi8RDkm+v4taLabb nOPTIEkUKNtuc4a6vJWiKK6oPkmNQRvrEAFFfFgl5Mp3CFTJVPUxSgeWu viY2YGMiQg7bTsP2Dy8fmyv9+HXL3AuR1d3ng6cR/YA8N0fJhVEVoUWDU itWmvcnQ98STBHlTT1pRKIgIz+NUm8jcD2CfZPQTxVwfzeI7WwBrpHqr1 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="312497997" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="312497997" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:44:03 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="638809863" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="638809863" Received: from ppkrause-mobl.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.249.44.73]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:43:59 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-fpga@vger.kernel.org, Xu Yilun , Wu Hao , Tom Rix , Moritz Fischer , Lee Jones , Matthew Gerlach , Russ Weight , Tianfei zhang , Mark Brown , Greg KH , linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 09/12] intel-m10-bmc: Add regmap_indirect_cfg for Intel FPGA IPs Date: Tue, 8 Nov 2022 16:43:02 +0200 Message-Id: <20221108144305.45424-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221108144305.45424-1-ilpo.jarvinen@linux.intel.com> References: <20221108144305.45424-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748939826956092327?= X-GMAIL-MSGID: =?utf-8?q?1748939826956092327?= Create the regmap_indirect_cfg with offsets and commands for Intel FPGA IPs indirect register access. Signed-off-by: Ilpo Järvinen Reviewed-by: Matthew Gerlach --- include/linux/mfd/intel-m10-bmc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index ed920f76d3c8..1b907c1a176f 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -15,6 +15,19 @@ enum m10bmc_type { M10_N5010, }; +#define INTEL_M10_REGMAP_INDIRECT_CFG \ + .cmd_offset = 0, \ + .idle_cmd = 0, \ + .read_cmd = BIT(0), \ + .write_cmd = BIT(1), \ + .ack_offset = 0, \ + .ack_mask = BIT(2), \ + .addr_offset = 0x4, \ + .read_offset = 0x8, \ + .write_offset = 0xc, \ + .sleep_us = 1, \ + .timeout_us = 10000 + #define M10BMC_STAGING_SIZE 0x3800000 /* Doorbell register fields */