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[37.212.12.58]) by smtp.gmail.com with ESMTPSA id p11-20020a05640210cb00b004637489cf08sm4994444edu.88.2022.11.07.20.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 20:53:56 -0800 (PST) From: Siarhei Volkau Cc: Siarhei Volkau , Paul Cercueil , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Ulf Hansson , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Subject: [PATCH 2/2] MIPS: ingenic: rs90: set MMC_MUX clock Date: Tue, 8 Nov 2022 07:53:00 +0300 Message-Id: <20221108045300.2084671-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221108045300.2084671-1-lis8215@gmail.com> References: <20221108045300.2084671-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748902686266861516?= X-GMAIL-MSGID: =?utf-8?q?1748902686266861516?= Since the MMC driver can't change the common MMC_MUX clock anymore, the CGU shall configure that clock properly. Signed-off-by: Siarhei Volkau --- arch/mips/boot/dts/ingenic/rs90.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/rs90.dts b/arch/mips/boot/dts/ingenic/rs90.dts index e8df70dd4..d874abaa6 100644 --- a/arch/mips/boot/dts/ingenic/rs90.dts +++ b/arch/mips/boot/dts/ingenic/rs90.dts @@ -295,8 +295,9 @@ partition@20000 { &cgu { /* Use 32kHz oscillator as the parent of the RTC clock */ - assigned-clocks = <&cgu JZ4725B_CLK_RTC>; - assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>; + assigned-clocks = <&cgu JZ4725B_CLK_MMC_MUX>, <&cgu JZ4725B_CLK_RTC>; + assigned-clock-parents = <0>, <&cgu JZ4725B_CLK_OSC32K>; + assigned-clock-rates = <48000000>; }; &tcu {