From patchwork Mon Nov 7 20:49:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 16728 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2308076wru; Mon, 7 Nov 2022 13:34:14 -0800 (PST) X-Google-Smtp-Source: AMsMyM5NvEcGMz71AKXHqUChB7xlTclSFe2PczLpYnGSxz9p6/aLb3ZzXqRx+Mc1QMK7Y4Q/lgAA X-Received: by 2002:a05:6402:1248:b0:461:fc07:b95b with SMTP id l8-20020a056402124800b00461fc07b95bmr52817976edw.56.1667856854221; Mon, 07 Nov 2022 13:34:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667856854; cv=none; d=google.com; s=arc-20160816; b=BLk/V6Mtvr5eZ0TorqvVIInPm1ZWDgd2Y7TRgIuG6lhDHaUrYt28rsuAEvc/xIx8fg 2QCGaNVQDRGFWs6PrbR91A5CZkplZ/7xYtISXvxX0hjzP9Baere7w0bg9+vHCnQXZHwz FU2ZZokyZ72p6O7yCOEP0YTxJ5Z94ONtnVr16puZIQzxy0TSErOPBoBUsZrKuvPalrZ3 X9bY2dHYTD67Ul3EMrSQjchBDyXEWnDKhIxWyXK4WxWYZjn83LKYADmXVukadXRaHyS5 vSSe4ahuFruvmhEl3IaQYmJAdi8lgrVDvG66T25/7cdHx+yNc/CA1fhXCQiNBUyB9uE7 u7iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZO2KozCesJXMnFVF7RMoOEcLvdjeR1lQvgddDu9E7xA=; b=YtjsGIxglFIV7HDN1seHBbHMgs16mEZ/GberPb8hecrM3Uv10oBwV+zsHX6+oRxlGO +TUT4hoEU9zPPHOmheRb+QBoL+O9T3t967+cA2opVDLAyArrzOt5nHrdSD1ogU/rki39 w4MZynx3MwkDFAeSmr4TnvAMIL5EOwysP2xi1NjWlMZ1hVtm1OZtNf5yaelWekgySC6w tS6tmBj6dAyGQ6SegeZzPzxAo+ODoDzwvYlMXHWebHoHESAJC9RosTBJaXqbE97BnOTZ vxqs1iKdf7SceP9CgPZdn3YLm959VI8KNfReBUpIQH+Eu0dULa4Js9fDM+nsM1l1ZoSW oKJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baikalelectronics.ru header.s=post header.b=pI0Ca+Cu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=baikalelectronics.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y25-20020a50e619000000b00461ebc19dcesi9714112edm.56.2022.11.07.13.33.50; Mon, 07 Nov 2022 13:34:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baikalelectronics.ru header.s=post header.b=pI0Ca+Cu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=baikalelectronics.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233328AbiKGV0Z (ORCPT + 99 others); Mon, 7 Nov 2022 16:26:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233227AbiKGV0K (ORCPT ); Mon, 7 Nov 2022 16:26:10 -0500 Received: from post.baikalelectronics.com (post.baikalelectronics.com [213.79.110.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B47F22ED78; Mon, 7 Nov 2022 13:26:02 -0800 (PST) Received: from post.baikalelectronics.com (localhost.localdomain [127.0.0.1]) by post.baikalelectronics.com (Proxmox) with ESMTP id BC317E0EB3; Mon, 7 Nov 2022 23:50:10 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= baikalelectronics.ru; h=cc:cc:content-transfer-encoding :content-type:content-type:date:from:from:in-reply-to:message-id :mime-version:references:reply-to:subject:subject:to:to; s=post; bh=ZO2KozCesJXMnFVF7RMoOEcLvdjeR1lQvgddDu9E7xA=; b=pI0Ca+Cu275k btMPAjqeWL59JgcwmLtyjrOfMIqxiYHykkNDRWcO608ZuQ/J6hEc5stMI2dcWn+x A9oc6PglnIbw+OsHccGoL/o71fHsGbqz8LSo9/gFrteqrgtklrbwLmzHbwNsNyj+ THu+Araju8bKoYqBXxx5tSDJ5k0eTuU= Received: from mail.baikal.int (mail.baikal.int [192.168.51.25]) by post.baikalelectronics.com (Proxmox) with ESMTP id A6316E0E1D; Mon, 7 Nov 2022 23:50:10 +0300 (MSK) Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Nov 2022 23:50:10 +0300 From: Serge Semin To: Rob Herring , Rob Herring , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Cai Huoqing , Robin Murphy , Jingoo Han , Gustavo Pimentel CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= , Frank Li , Manivannan Sadhasivam , caihuoqing , Vinod Koul , , , Subject: [PATCH v6 05/20] dt-bindings: PCI: dwc: Add phys/phy-names common properties Date: Mon, 7 Nov 2022 23:49:19 +0300 Message-ID: <20221107204934.32655-6-Sergey.Semin@baikalelectronics.ru> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221107204934.32655-1-Sergey.Semin@baikalelectronics.ru> References: <20221107204934.32655-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-Originating-IP: [192.168.168.10] X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748874668671229288?= X-GMAIL-MSGID: =?utf-8?q?1748874668671229288?= It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit PHY phandle references. There can be up to 16 PHYs attach in accordance with the maximum number of supported PCIe lanes. Let's extend the common DW PCIe controller schema with the 'phys' and 'phy-names' properties definition. There two types PHY names are defined: preferred generic names '^pcie[0-9]+$' and non-preferred vendor-specific names '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6; "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d": keystone, dra7xx; "pcie": histb, etc). Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v3: - This is a new patch unpinned from the next one: https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/ by the Rob' request. (@Rob) Changelog v5: - Add a note about having line-based PHY phandles order. (@Rob) - Prefer 'pcie[0-9]+' PHY-names over the rest of the cases. (@Rob) Changelog v6: - Add the Nvidia Tegra194-specific "p2u-[0-7]" phy-names too. (@DT-tbot) - Drop 'deprecated' keywords from the vendor-specific names. (@Rob) --- .../bindings/pci/snps,dw-pcie-common.yaml | 24 +++++++++++++++++++ .../bindings/pci/snps,dw-pcie-ep.yaml | 3 +++ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 3 +++ 3 files changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index 554c2804c608..91d24e400dfc 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -17,6 +17,30 @@ description: select: false properties: + phys: + description: + There can be up to the number of possible lanes PHYs specified placed in + the phandle array in the line-based order. Obviously each the specified + PHYs are supposed to be able to work in the PCIe mode with a speed + implied by the DWC PCIe controller they are attached to. + minItems: 1 + maxItems: 16 + + phy-names: + minItems: 1 + maxItems: 16 + oneOf: + - description: Generic PHY names + items: + pattern: '^pcie[0-9]+$' + - description: + Vendor-specific PHY names. Consider using the generic + names above for new bindings. + items: + oneOf: + - pattern: '^pcie(-?phy[0-9]*)?$' + - pattern: '^p2u-[0-7]$' + reset-gpio: deprecated: true description: diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 7d05dcba419b..dcd521aed213 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -52,4 +52,7 @@ examples: <0xdfc01000 0x0001000>, /* IP registers 2 */ <0xd0000000 0x2000000>; /* Configuration space */ reg-names = "dbi", "dbi2", "addr_space"; + + phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>; + phy-names = "pcie0", "pcie1", "pcie2", "pcie3"; }; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 3fdc80453a85..d9512f7f7124 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -70,5 +70,8 @@ examples: reset-gpios = <&port0 0 1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + num-lanes = <1>; };