From patchwork Mon Nov 7 17:56:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 16622 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2206994wru; Mon, 7 Nov 2022 10:06:06 -0800 (PST) X-Google-Smtp-Source: AMsMyM6OsPk0clPY+aL4BUNlN1UKdcoGrGtLUiOjbiRzXuqyq7F4LJ5V3h6tKOPNapF02xcHU+7o X-Received: by 2002:a05:6402:3457:b0:463:2017:ae64 with SMTP id l23-20020a056402345700b004632017ae64mr47933120edc.218.1667844365863; Mon, 07 Nov 2022 10:06:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1667844365; cv=pass; d=google.com; s=arc-20160816; b=oxHW75wk93YukskaCm7IZLKpPIJ2nbOkjuxOOFOugEusSM9KF8loxYJe8+O6tD8HG/ l3LxZQr2kN16QtkLoyqoAi1+2IZ3Pi4L9lfmkTGWKwdiGQP+lqFoXHzwIXQzyqaC0mA8 kG4EkHWlJ+2lUVSnKJ7xQmBXF8Nf6IpqvTIGqVBXrYs0UqkD2OugpTujYMWN6QFNB/wt TsmIPvgNTQ3hWGrcRX/1VTpcGxj6iTdCi7aTBhAYBF7urUnYSPBn6VTpImfK+92UdFAS 61ARrQPvo9LMmH4wZLCfRQMMgW9D8Obuv9nCcDo/i3OPtb/O/hTDBZl9ilMeXiwk8Ayr iXHg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cmio7gJqwKhbNrAkIoLPDLjcBv05TysnwpTuYzfUpac=; b=VI6G33dGZy1Jcx2G2kjl5A461JVJLdtk747DmcG6dWGYFZHt9H5yC9bqWvLQbsKXGH mny6vCW7eTn9M7dgMcvAvRSSOAZUcdV10RfWkSvdWkdp/gBERCgSK0B7GQ1w86poRX9d tR8pu+KKpn2vhjqqy2B3ajvvpUJC0CctCKfcXwOlwSmhFoXN3f11wkzf4KOig02oNQ03 zsM+W3cTVHngoesSj5AuuCFE5q9O4JasCTaG0kkxxNkT1J8ME17ZTFfzvC9dfAv/iztB /G9nZV1sbyiImu4vBARooaZAE3OlefmcnBPMHNh71N68rkg0OfTuawidm4oxs2iChneG Y+jw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=scJzBVsn; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c12-20020a056402120c00b004615a57e292si8145192edw.426.2022.11.07.10.05.42; Mon, 07 Nov 2022 10:06:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=scJzBVsn; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232760AbiKGSCl (ORCPT + 99 others); Mon, 7 Nov 2022 13:02:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233125AbiKGSB6 (ORCPT ); Mon, 7 Nov 2022 13:01:58 -0500 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2062.outbound.protection.outlook.com [40.107.237.62]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E67BFF03; Mon, 7 Nov 2022 09:58:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WV5+d5KIkiKlJR60eipMs9JC2h969KXgVl6gLW4yuvm9nGQcwL1baT3cbwM7JD/Gvgx6eZI5FMzAMn9fM81DtBV1vhw85Wr7khXExmNPN8GN0+45rqML1Ole5OnbhNRboaOXIciHj2rkPbIdCSUBen9N08uzU2dgf1nxgzXKWDUaQ14icjvsGfW1NY5vfQwgXl3P4hePQgkgKzUBq9eeoihVLnfdBBQvTU00vJ1xQEI+cjzqF3/7GHqVH+YZ58WUf1NTgP69EFZTQjqDs3XFAJzSn9hmpo5RyKCI0SZ/P+5ek/F3Lj4+y8/3JiHxfjV7/RSyxFAfz8c8+BnKtv2ejQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cmio7gJqwKhbNrAkIoLPDLjcBv05TysnwpTuYzfUpac=; b=cWFSGVBbpIJNfEDFLTWmLW+Wvg5N2rnxmPT31BwQCkbtmevJ97u54kKHmxJXsqDp1Q5RjhiZU4OoFvV2+WR6iH60u3NVsDg8vXwxSobZ/5cu2C2cmkjRimTANjPcOfBwfhSCRWAhdPQ3FZMx873EvtTS77/HyghCvsFz28abzDqLA9PkX8OpH5DVK08xVtLYZjscRa2qjo0cUv/vSbIePJrDBbFULkeZBbrwWd5kIQKOpBKrcjRWmZYhm4LDZaraRfP2z5MVV2+dz6w0Ad2dsVEgC3YxO7Ya7LbprSBq9M8MtGQN77WB4cPIPIxdioAL0zgOYgon22Xsbt7pfnUMqQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cmio7gJqwKhbNrAkIoLPDLjcBv05TysnwpTuYzfUpac=; b=scJzBVsniCWoBRTQk88hZPvdgEIexDxDK5sEO83t3n3CuLpIFos3N4abNX+ovPOvqQumKz/jZNkOHeuAvxCb4JH2xANR6X67XbShrYqwjrqASpEhMO9wEGODYuHFR1deRAvTUkAc2BFD+sPWfXljDGsl4YahoWJidYn2trVn0z8= Received: from DS7PR05CA0034.namprd05.prod.outlook.com (2603:10b6:8:2f::35) by BL3PR12MB6379.namprd12.prod.outlook.com (2603:10b6:208:3b2::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.26; Mon, 7 Nov 2022 17:57:59 +0000 Received: from DM6NAM11FT033.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2f:cafe::1f) by DS7PR05CA0034.outlook.office365.com (2603:10b6:8:2f::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.9 via Frontend Transport; Mon, 7 Nov 2022 17:57:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT033.mail.protection.outlook.com (10.13.172.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Mon, 7 Nov 2022 17:57:59 +0000 Received: from pyuan-Cloudripper.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 7 Nov 2022 11:57:55 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Date: Tue, 8 Nov 2022 01:56:58 +0800 Message-ID: <20221107175705.2207842-2-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT033:EE_|BL3PR12MB6379:EE_ X-MS-Office365-Filtering-Correlation-Id: 20428671-2beb-43cf-3d16-08dac0e99b5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AdYbMo3fy7wOwB8g3Aoc1rd95bqLKVJxUMCmcHgQ1KZ59aFd39CVdYbQU1g6tqHGOaldXqa9j+Rk53C7WEy3kpci3wZ0MBIjzNA77ZMT4Kca9LEVBPwRcrEbgVbmrkE+hWQ/yDifkOipmUzl/64HuXjt1Nhqi2p83+nIObNDo0QbGujBQrFQZkdbyzE+Qs2fgMYTFYspOjarLoekaOKOl4xVrS8IJr1WQX/GfU8bWwdFArJKraAoe4ycD3f6Yx2eRE8ZIebH88XZa3EiEGAqKiNeYLJKbqHwttZXpbC8KSoGlaYTV8c0ZWJ1YJjZigpgOlQGKJ3lycvPwdVc2qK0K+5tpPH7lTRTzwwnLUsLvWN6Pcl/txnMX5u8zfPJcEEKia7xB1IAox3uT9T6xfQtL9JIxT7pRl0uKowDDLnxgfTa0+AQfqxjxyULIFBeYGLJj6cDBKk4E/GomnbFrMMRXtYfLPFM6F9R52FGSncliv7LdsiRoM4aMpPgHbH87cCLS0jggnOv/o+k+4C0CfhgymXaD7qKAfbMV0vuA7P1bJbpXxkIxMiRZdsN8+o7sKufAgQPG2bK0SKbswaE/V7zZqSLC54ml1z8YUIp95WgfqORbzUE0fGQf/g6VPhh+waXih7JLHF14d/yF9LZRFhv/gc+6K3u7bt5tzfQyuAjW6ZeL+/du/MSUJ1WEbXB4UpAtALtCA9CU7QDjV+Cx8pl0BFZr6iRk8cVbnN0vBpYYP18qvS5T5OAExffCzI0eJDM2LpCFDn/YDGipb+1VTr112xlenmt8IRQAZCx/dFMsmAatKWdKiLw0MkcZSFEV9nyY1kSwzW4g5zGo99pWOJMiQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(40480700001)(86362001)(16526019)(81166007)(41300700001)(356005)(110136005)(316002)(8676002)(8936002)(4326008)(70586007)(54906003)(70206006)(36860700001)(5660300002)(40460700003)(82740400003)(478600001)(186003)(336012)(1076003)(83380400001)(7696005)(26005)(82310400005)(2616005)(426003)(47076005)(2906002)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:57:59.1835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20428671-2beb-43cf-3d16-08dac0e99b5c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6379 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861573806262744?= X-GMAIL-MSGID: =?utf-8?q?1748861573806262744?= Add the EPP(Energy Performance Preference) support for the AMD SoCs without the dedicated CPPC MSR, those SoCs need to add this cppc acpi functions to update EPP values and desired perf value. In order to get EPP worked, cppc_get_epp_caps() will query EPP preference value and cppc_set_epp_perf() will set EPP new value. Before the EPP works, pstate driver will use cppc_set_auto_epp() to enable EPP function from firmware firstly. Signed-off-by: Perry Yuan --- drivers/acpi/cppc_acpi.c | 126 +++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 17 ++++++ 2 files changed, 143 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 093675b1a1ff..d9c38dee1f48 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_get_epp_caps - Get the energy preference register value. + * @cpunum: CPU from which to get epp preference level. + * @perf_caps: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *energy_perf_reg; + u64 energy_perf; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (!CPC_SUPPORTED(energy_perf_reg)) + pr_warn("energy perf reg update is unsupported!\n"); + + if (CPC_IN_PCC(energy_perf_reg)) { + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0; + + if (pcc_ss_id < 0) + return -ENODEV; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { + cpc_read(cpunum, energy_perf_reg, &energy_perf); + perf_caps->energy_perf = energy_perf; + } else { + ret = -EIO; + } + + up_write(&pcc_ss_data->pcc_lock); + + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_epp_caps); + +int cppc_set_auto_epp(int cpu, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) + return -ENODEV; + + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + return ret; + } + + return cpc_write(cpu, auto_sel_reg, enable); +} +EXPORT_SYMBOL_GPL(cppc_set_auto_epp); + +/* + * Set Energy Performance Preference Register value through + * Performance Controls Interface + */ +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *epp_set_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (CPC_IN_PCC(epp_set_reg)) { + if (pcc_ss_id < 0) + return -ENODEV; + + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c5614444031f..10d91aeedaca 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -108,12 +108,14 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; + u32 energy_perf; }; struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void); extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); +extern int cppc_set_auto_epp(int cpu, bool enable); +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { return -ENOTSUPP; } +static inline int cppc_set_auto_epp(int cpu, bool enable) +{ + return -ENOTSUPP; +} +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + return -ENOTSUPP; +} +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + return -ENOTSUPP; +} #endif /* !CONFIG_ACPI_CPPC_LIB */ #endif /* _CPPC_ACPI_H*/