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Subject: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
Date: Mon, 7 Nov 2022 16:57:13 +0100
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| Series |
Update cache properties for arm64 DTS
|
|
Commit Message
Pierre Gondois
Nov. 7, 2022, 3:57 p.m. UTC
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
3 files changed, 4 insertions(+)
Comments
(subset for cc list) Hello, Just a reminder in case the patch was forgotten, Regards, Pierre On 11/7/22 16:57, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > The 'cache-unified' property should be present if one of the > properties for unified cache is present ('cache-size', ...). > > Update the Device Trees accordingly. > > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> > --- > arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 + > arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ > arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + > 3 files changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > index 1c76b4375b2e..6e1e00939214 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > @@ -52,6 +52,7 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > index 9308458f9611..db7d20a1a301 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > @@ -86,10 +86,12 @@ cpu3: cpu@101 { > > a72_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > }; > > a53_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > index b0c29510a7da..9ce544c9ea0a 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > @@ -83,6 +83,7 @@ cpu3: cpu@3 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; >
Hi Pierre, On 2023/01/12 17:33, Pierre Gondois wrote: > (subset for cc list) > Hello, > Just a reminder in case the patch was forgotten, > Regards, > Pierre > > On 11/7/22 16:57, Pierre Gondois wrote: >> The DeviceTree Specification v0.3 specifies that the cache node >> 'compatible' and 'cache-level' properties are 'required'. Cf. >> s3.8 Multi-level and Shared Cache Nodes >> The 'cache-unified' property should be present if one of the >> properties for unified cache is present ('cache-size', ...). >> >> Update the Device Trees accordingly. >> >> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> >> --- >> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 + >> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ >> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + >> 3 files changed, 4 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi >> b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi >> index 1c76b4375b2e..6e1e00939214 100644 >> --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi >> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi >> @@ -52,6 +52,7 @@ cpu1: cpu@1 { >> >> l2: l2-cache { >> compatible = "cache"; >> + cache-level = <2>; >> }; >> }; >> >> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi >> b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi >> index 9308458f9611..db7d20a1a301 100644 >> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi >> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi >> @@ -86,10 +86,12 @@ cpu3: cpu@101 { >> >> a72_l2: l2-cache0 { >> compatible = "cache"; >> + cache-level = <2>; >> }; >> >> a53_l2: l2-cache1 { >> compatible = "cache"; >> + cache-level = <2>; >> }; >> }; >> >> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi >> b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi >> index b0c29510a7da..9ce544c9ea0a 100644 >> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi >> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi >> @@ -83,6 +83,7 @@ cpu3: cpu@3 { >> >> l2: l2-cache { >> compatible = "cache"; >> + cache-level = <2>; >> }; >> }; >> Looks good to me. "cache-unified" will be added with other cache-related (size etc.) properties if needed. Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Thank you, --- Best Regards Kunihiko Hayashi
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 1c76b4375b2e..6e1e00939214 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 9308458f9611..db7d20a1a301 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,12 @@ cpu3: cpu@101 { a72_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index b0c29510a7da..9ce544c9ea0a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; };