[v2,10/23] arm64: dts: Update cache properties for lg

Message ID 20221107155825.1644604-11-pierre.gondois@arm.com
State New
Headers
Series Update cache properties for arm64 DTS |

Commit Message

Pierre Gondois Nov. 7, 2022, 3:57 p.m. UTC
  The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
 arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
 arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
 2 files changed, 2 insertions(+)
  

Comments

Pierre Gondois Jan. 12, 2023, 8:34 a.m. UTC | #1
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre

On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
> 
> Update the Device Trees accordingly.
> 
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
>   arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
>   arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
> index 78ae73d0cf36..25ed9aeee2dc 100644
> --- a/arch/arm64/boot/dts/lg/lg1312.dtsi
> +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>   		};
>   		L2_0: l2-cache0 {
>   			compatible = "cache";
> +			cache-level = <2>;
>   		};
>   	};
>   
> diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
> index 2173316573be..db82fd4cc759 100644
> --- a/arch/arm64/boot/dts/lg/lg1313.dtsi
> +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>   		};
>   		L2_0: l2-cache0 {
>   			compatible = "cache";
> +			cache-level = <2>;
>   		};
>   	};
>
  
Chanho Min Jan. 13, 2023, 1:12 a.m. UTC | #2
23. 1. 12. 오후 5:34에 Pierre Gondois 이(가) 쓴 글:
> (subset for cc list)
> Hello,
> Just a reminder in case the patch was forgotten,
> Regards,
> Pierre
> 
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Acked-by: Chanho Min <chanho.min@lge.com>
>> ---
>>   arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
>>   arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
>>   2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi 
>> b/arch/arm64/boot/dts/lg/lg1312.dtsi
>> index 78ae73d0cf36..25ed9aeee2dc 100644
>> --- a/arch/arm64/boot/dts/lg/lg1312.dtsi
>> +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
>> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>>           };
>>           L2_0: l2-cache0 {
>>               compatible = "cache";
>> +            cache-level = <2>;
>>           };
>>       };
>> diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi 
>> b/arch/arm64/boot/dts/lg/lg1313.dtsi
>> index 2173316573be..db82fd4cc759 100644
>> --- a/arch/arm64/boot/dts/lg/lg1313.dtsi
>> +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
>> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>>           };
>>           L2_0: l2-cache0 {Re: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
>>               compatible = "cache";
>> +            cache-leveRe: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lgl = <2>;
>>           };
>>       };
  

Patch

diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 78ae73d0cf36..25ed9aeee2dc 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -48,6 +48,7 @@  cpu3: cpu@3 {
 		};
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 2173316573be..db82fd4cc759 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -48,6 +48,7 @@  cpu3: cpu@3 {
 		};
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};