From patchwork Mon Nov 7 12:45:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 16401 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2034968wru; Mon, 7 Nov 2022 05:04:21 -0800 (PST) X-Google-Smtp-Source: AMsMyM4agnDzbspImolz0Nn36PiBpv6uE8ODsUchBHPv2ipX/oMaTG5CYoBhGgkFiP7mdFuT/ZFi X-Received: by 2002:a17:902:7593:b0:188:584e:cbfd with SMTP id j19-20020a170902759300b00188584ecbfdmr22420716pll.64.1667826260761; Mon, 07 Nov 2022 05:04:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667826260; cv=none; d=google.com; s=arc-20160816; b=Oq6N9r/rxVS8fP1Il5z9WsQjieoONjvN9B1TJoZhf5kT03Y5J9apRCy373HdQKRVPg 5TCiTWUc+P8nxRQhKCNfuusD906JmcOfqKH0QEELJIZTkAZFLRkabcAYjzlfwl/NWhgQ rk78ButjvQUSR88Rw/4CXv9h5mvVdEUu4ZymQbqvYNht3VXHMXC8Pe8W8NhAaq2HpLND pt7Glar4g+O80tyZFCDCqLNu5TJH4Z+e15lfXOvPbsTYMgnoW3db4Yg/g/2Og/q+XDuS u2PiP6CZcvfBRzHBLdC9XCIhKkHfFJVeVsWgOpgR2yKB7w+4yhyLmuFiDhdpsy+bTnjv /jCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gCq0qRg7W1hb9I+p7/5D1lIDXZGuhYBgDRk3TnBdhVs=; b=H1JW3pads+1rcltNKtEmshXZ08w0Iq2Uuyn/Rk8jaecaEVVp5HpkzC9XqP8VxQHsy9 kbKrEm85TeHEieqVzWtc3SWCxt7+R6nrJK2q7DWfKn2ppVNwv3T1GaOREph6x3LIMRy8 EaaIJ1PHOuRkHOOPFZiVDeZLgY8jPMc7CIdafGushVGZV6DuFPXZjr4NdtSmHJbgq61n CtB8EWTP+b68Hy72YnCxR3/DVLNLTFM+NhB4U2AiegD0/fLzJlY5vOXvwAWpezkRm+Wz NHR1Cn3n6hA3Ou0Al2pqUQqhMVuV8unqMbIOVkpel92ZuBxqJNhFsTck3if6i5ze5Kyb nNKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=uAsQ8QHZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q19-20020a170902789300b0017f802fcffesi9784453pll.410.2022.11.07.05.04.03; Mon, 07 Nov 2022 05:04:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=uAsQ8QHZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232369AbiKGMps (ORCPT + 99 others); Mon, 7 Nov 2022 07:45:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232356AbiKGMpb (ORCPT ); Mon, 7 Nov 2022 07:45:31 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 380A31BEAA; Mon, 7 Nov 2022 04:45:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1667825131; x=1699361131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1g3ZoLeTzd5buYYEiRhNgZ+0cPrzHWqcCAwXMPpYlQQ=; b=uAsQ8QHZ7miCXKeDd1th2+CcJJ+nXzT041tA4YNLD8BcGF6YITlDFYMG hrwNrGxgFJxzG0nkyEiJKclmdy64+dkQJyInE5OvbDLOsalt2izHddgj7 2irL+dpoVhborzxm7uN1lNxFpGGO1K5VrtRGTBuKHVM4gONBrj3mE57XF 0NSNiM1noircE6DzJGHJoYdO6ZKcg2khpFFW0fu4R4qAKxk3VgVjrzQG8 20NOkXrzcGjTjtwhg48cU9WJUveA3+lVM8mntXoQKWHw+0bhQij9kfNBg q8Yzrd/ro2qitRy9LQ1tjwXxpzOauYz5/KGXXrZIO3nuD3MUGp4kz5dpF w==; X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="182255428" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Nov 2022 05:45:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 7 Nov 2022 05:45:29 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 7 Nov 2022 05:45:23 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v3 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485 support to quad-uart driver Date: Mon, 7 Nov 2022 18:15:16 +0530 Message-ID: <20221107124517.1364484-3-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221107124517.1364484-1-kumaravel.thiagarajan@microchip.com> References: <20221107124517.1364484-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748842589119920660?= X-GMAIL-MSGID: =?utf-8?q?1748842589119920660?= pci1xxxx uart supports rs485 mode of operation in the hardware with auto-direction control with configurable delay for releasing RTS after the transmission. This patch adds support for the rs485 mode. Signed-off-by: Kumaravel Thiagarajan Signed-off-by: Tharun Kumar P --- Changes in v3: - Remove flags sanitization in driver which is taken care in core Changes in v2: - move pci1xxxx_rs485_config to a separate patch with pci1xxxx_rs485_supported. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index e74e8d63daee..ed3418feb262 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -137,6 +137,53 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, port->membase + UART_BAUD_CLK_DIVISOR_REG); } +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + u8 delay_in_baud_periods = 0; + u32 baud_period_in_ns = 0; + u32 data = 0; + + /* pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + data |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + (rs485->delay_rts_after_send * NSEC_PER_MSEC) / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u8, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + (baud_period_in_ns * delay_in_baud_periods) / + NSEC_PER_MSEC; + rs485->delay_rts_before_send = 0; + } + } + writel(data, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int idx) { @@ -186,6 +233,8 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; ret = pci_setup_port(priv->dev, port, 0, offset, 0); if (ret < 0) return ret;