From patchwork Sun Nov 6 03:39:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mengqi Zhang X-Patchwork-Id: 16063 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1309087wru; Sat, 5 Nov 2022 21:05:34 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7kHCNFDW38MQvrNyn44OGBUpZNlf+qdUXJK2AgqAPcv7lAyEPpAC5TcmCmlkJwr13ACOR7 X-Received: by 2002:a17:906:9d14:b0:799:9ace:e868 with SMTP id fn20-20020a1709069d1400b007999acee868mr528975ejc.451.1667707534066; Sat, 05 Nov 2022 21:05:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667707534; cv=none; d=google.com; s=arc-20160816; b=xhCHanGo6xKMNaD6HeqKWb5PMVvSB3R4el3vEeRBxb8LCvzPCA4yw1Mo7hmKyEjtK5 HabC4TG4rQ2MyDcDAlDlyrDrHZxMwCces3k7fqNEtRD89stXiGi+ossaw4vNduaPSbRX QXIfawLCl6hmOPaHmd4rL3n8DJmq3OofxRTDiDAbXoCL/rz/iBuL8OpGz7O3Q2zQfH9U qgdtkiQ2ecnW9ILqJP7etLIzUCbWyY9pZ2es7gsEOb1CWpSNWIQR8BwYyevR/GZSqZOL JdZQ+e9eHdTimlOP/LWf4B1UXcbAKbVcsQP9uRa/JZm3sLKx+ba4jWbd4LUS/bIGehM+ 68Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dz2mheJDfObycJwcc1Bk8TmgsLqq6x+ImrkrFILsGBU=; b=zutN0Z+z3YIcYgVdDdlPn80yk1OsbVXHJBsBgA6aRkq6Of43acihzwg/90BP3UqLcP ASyHu/L7C+AHAe8YFoXRDGD4LRzqdBbJ7ykn+cLnZCtGx3WT4kUxvarsCnsg6KuI4FGa u710aVyVWpQKYzus9o+mxcEYqAddqAsfCtiQhWTw+s9UMBFubdc7GeGTK/MNNf8apzmr FJbgZG+adQzaYmZOvUxvdPFPDc5kqsjwiKmvY7UU/+j93PNlQQ1fNaca7OWU4JBFUD3t gVh3w0/n4ZF8cwXKTNvuVk7KDqYkr6U3csi8OrDN/JU4OpLWCLUTJgz3/cOnmkrmTA1K yASA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=EQ9dWJKA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v18-20020a1709061dd200b0079ca59305a6si3529259ejh.354.2022.11.05.21.04.57; Sat, 05 Nov 2022 21:05:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=EQ9dWJKA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229678AbiKFDkS (ORCPT + 99 others); Sat, 5 Nov 2022 23:40:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229547AbiKFDkQ (ORCPT ); Sat, 5 Nov 2022 23:40:16 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 062A1C75E; Sat, 5 Nov 2022 20:40:14 -0700 (PDT) X-UUID: 08aac0423735415ead2c733b63bb463f-20221106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dz2mheJDfObycJwcc1Bk8TmgsLqq6x+ImrkrFILsGBU=; b=EQ9dWJKA8DZWU1A8AqxqKdlm5H3HZBmJuDJOK9FR/Ax/KIr1UYp3qQ/u5eXnUbBwntZD3Xn/vh+yxFI7Uu5EhEKOxcfef0EUfUFfuR2b843XRIUe3k4bbpsfcJwggn3e4js4pzmseQi/I5Cwvf+qVnyHKKi277s5bJDofR8+MR8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:541ddcc8-6027-48e8-90ec-4ac15b9e2825,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:62cd327,CLOUDID:6be18beb-84ac-4628-a416-bc50d5503da6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 08aac0423735415ead2c733b63bb463f-20221106 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 542255528; Sun, 06 Nov 2022 11:40:10 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sun, 6 Nov 2022 11:40:08 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sun, 6 Nov 2022 11:40:08 +0800 From: Mengqi Zhang To: , , , , , , , CC: , , , , Subject: [RESEND v2 1/2] mmc: mtk-sd: add Inline Crypto Engine clock control Date: Sun, 6 Nov 2022 11:39:24 +0800 Message-ID: <20221106033924.9854-2-mengqi.zhang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221106033924.9854-1-mengqi.zhang@mediatek.com> References: <20221106033924.9854-1-mengqi.zhang@mediatek.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748718095491213099?= X-GMAIL-MSGID: =?utf-8?q?1748718095491213099?= Add crypto clock control and ungate it before CQHCI init. Signed-off-by: Mengqi Zhang Reviewed-by: AngeloGioacchino Del Regno --- drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 3f7f3a1e0df8..652a67f9b054 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -452,6 +452,7 @@ struct msdc_host { struct clk *bus_clk; /* bus clock which used to access register */ struct clk *src_clk_cg; /* msdc source clock control gate */ struct clk *sys_clk_cg; /* msdc subsys clock control gate */ + struct clk *crypto_clk; /* msdc crypto clock control gate */ struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; u32 mclk; /* mmc subsystem clock frequency */ u32 src_clk_freq; /* source clock frequency */ @@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) static void msdc_gate_clock(struct msdc_host *host) { clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); + clk_disable_unprepare(host->crypto_clk); clk_disable_unprepare(host->src_clk_cg); clk_disable_unprepare(host->src_clk); clk_disable_unprepare(host->bus_clk); @@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc_host *host) clk_prepare_enable(host->bus_clk); clk_prepare_enable(host->src_clk); clk_prepare_enable(host->src_clk_cg); + clk_prepare_enable(host->crypto_clk); ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); if (ret) { dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); @@ -2672,6 +2675,15 @@ static int msdc_drv_probe(struct platform_device *pdev) goto host_free; } + /* only eMMC has crypto property */ + if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { + host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); + if (IS_ERR(host->crypto_clk)) + host->crypto_clk = NULL; + else + mmc->caps2 |= MMC_CAP2_CRYPTO; + } + host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = -EINVAL;