From patchwork Sat Nov 5 14:59:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 15980 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1034691wru; Sat, 5 Nov 2022 08:04:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM59v37YNemzx+imKL7fVp8Pg5zs7Y1HzTXnjasWAKmcLLhIJpUIJ1dP2AJH/MLuaqRUmwI4 X-Received: by 2002:a17:902:b945:b0:181:c6b6:abc with SMTP id h5-20020a170902b94500b00181c6b60abcmr41120225pls.75.1667660643797; Sat, 05 Nov 2022 08:04:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667660643; cv=none; d=google.com; s=arc-20160816; b=nRDSHNatLRM7HFvsZ+9iUZv3TFFVg86JgGw+erKQwxLOJj8xcXnViui9sFZmKWh0cl c+trwnxt1gWvHW5gAWbu1dIUVDBoIgZyt0cXztRXUVx4gIZHvTyhBobs7RhEcWx02tou i0T5bFH5TvNt/Tf1+ZV6KD4EgmCH5cImV3Lr6tkDusHjzyJXImilHJrK2+AYE9mBhSQY cpnwUnQccoAz8AeEdwjydDgea7le9t8GuMD520LB8NhHXX7+zWIM+j4jnXaHrc9PM15U fakT9d5axHTt3VAnoQEFskH/+I7WaUvlEyK4Ho4J6wD3MMva3fJu6NKqWe4dO/U9Qvss L4cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Dgcp3UzELuxZiasdkaiCr4rYe1WtZzLbiBi0e/RNEb4=; b=E9iKOestIQrssjiBKqaV9CfdK4zy5T525an3gpEQCq/2oC5m1hlGbbV3W2C3YQpH/3 DEZtaLmBi4uZKivlO+xw7tzskpZ6fNVRzKBp0+w8Vjlsmd6JaE7jeG3Oizeagv2mcFrF XfCS2scapT/G49fRtB7EKltOPjIpdXCsjZImy/DX39SML26o7wllslXzzaFfiNxlxso8 5CjcrAocLxQVYydk9LVY/98nnOMGTqLLxCSBFSpthbikAOxIIQJuuEbxGE2CWVtoPB6I LIwq3dnl7JKFj5zCb6Z8ThDWoMbUJaMpo2Ryd6f5J/yuURQK2BjkupXIR6uqhzkew8pU 9DRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dpzR3cQo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y19-20020a1709027c9300b00186881e1ff0si2920654pll.302.2022.11.05.08.03.48; Sat, 05 Nov 2022 08:04:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dpzR3cQo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229939AbiKEPDH (ORCPT + 99 others); Sat, 5 Nov 2022 11:03:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229828AbiKEPCx (ORCPT ); Sat, 5 Nov 2022 11:02:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D283F10574; Sat, 5 Nov 2022 08:02:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6EFBB60AF0; Sat, 5 Nov 2022 15:02:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7CDFDC4315F; Sat, 5 Nov 2022 15:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667660570; bh=oVZOTzq45reHyMUZv3CzKzfVdLviOUal1dPut+RcE50=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dpzR3cQojso4N00J1Jx18hOHXzZGo4acBogaoMKYI5uvDVmeSLUWm3uR9BuZ/3LJc j3wzbR9AVrIZH+yNhahBHwDUbrs9YOaO2lM2J2zIw8jQoPI5Udq3mOPqo63R2AA04o 7hPIwu5quonuQqp5LIh6JNg95HypYb+gGBbDbLp1wMWaQtddUyyrLW+2SNFzQSeNN8 +LS9a3xiwnFC1qriAtr5SBmnz8l3knXllzafLOQzQ4g6fxB9wutDFNsxmkeATsyUVr te5laE5Cw0gD4emE+cDIo9YmvUoskHcqjKQw0QSGxjqFiavoF01m/vBgQWvRFZcdCZ DAf6QEojcrzlA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1orKgp-0005Kd-FS; Sat, 05 Nov 2022 16:02:31 +0100 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Dmitry Baryshkov Subject: [PATCH v5 09/16] phy: qcom-qmp-pcie: add register init helper Date: Sat, 5 Nov 2022 15:59:32 +0100 Message-Id: <20221105145939.20318-10-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221105145939.20318-1-johan+linaro@kernel.org> References: <20221105145939.20318-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748668927139370825?= X-GMAIL-MSGID: =?utf-8?q?1748668927139370825?= Generalise the serdes initialisation helper so that it can be used to initialise all the PHY registers (e.g. serdes, tx, rx, pcs). Note that this defers the ungating of the PIPE clock somewhat, which is fine as it isn't needed until starting the PHY. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 37 +++++------------------- 1 file changed, 8 insertions(+), 29 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index a977f2bbd831..09999d5b5268 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1820,27 +1820,22 @@ static void qmp_pcie_configure(void __iomem *base, qmp_pcie_configure_lane(base, tbl, num, 0xff); } -static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) -{ - void __iomem *serdes = qmp->serdes; - - if (!tbls) - return; - - qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); -} - -static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) +static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *serdes = qmp->serdes; void __iomem *tx = qmp->tx; void __iomem *rx = qmp->rx; void __iomem *tx2 = qmp->tx2; void __iomem *rx2 = qmp->rx2; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; if (!tbls) return; + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); @@ -1848,15 +1843,6 @@ static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_t qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); } -} - -static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) -{ - void __iomem *pcs = qmp->pcs; - void __iomem *pcs_misc = qmp->pcs_misc; - - if (!tbls) - return; qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); @@ -1932,8 +1918,8 @@ static int qmp_pcie_power_on(struct phy *phy) else mode_tbls = cfg->tbls_ep; - qmp_pcie_serdes_init(qmp, &cfg->tbls); - qmp_pcie_serdes_init(qmp, mode_tbls); + qmp_pcie_init_registers(qmp, &cfg->tbls); + qmp_pcie_init_registers(qmp, mode_tbls); ret = clk_prepare_enable(qmp->pipe_clk); if (ret) { @@ -1941,13 +1927,6 @@ static int qmp_pcie_power_on(struct phy *phy) return ret; } - /* Tx, Rx, and PCS configurations */ - qmp_pcie_lanes_init(qmp, &cfg->tbls); - qmp_pcie_lanes_init(qmp, mode_tbls); - - qmp_pcie_pcs_init(qmp, &cfg->tbls); - qmp_pcie_pcs_init(qmp, mode_tbls); - /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);