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The PV lock structure of the guest is allocated by user space. A hypercall interface is provided for the guest to interrogate the location of the shared memory structures. Signed-off-by: Zengruan Ye Signed-off-by: Usama Arif --- Documentation/virt/kvm/arm/index.rst | 1 + Documentation/virt/kvm/arm/pvlock.rst | 52 +++++++++++++++++++++++++ Documentation/virt/kvm/devices/vcpu.rst | 25 ++++++++++++ 3 files changed, 78 insertions(+) create mode 100644 Documentation/virt/kvm/arm/pvlock.rst diff --git a/Documentation/virt/kvm/arm/index.rst b/Documentation/virt/kvm/arm/index.rst index e84848432158..b8499dc00a6a 100644 --- a/Documentation/virt/kvm/arm/index.rst +++ b/Documentation/virt/kvm/arm/index.rst @@ -10,4 +10,5 @@ ARM hyp-abi hypercalls pvtime + pvlock ptp_kvm diff --git a/Documentation/virt/kvm/arm/pvlock.rst b/Documentation/virt/kvm/arm/pvlock.rst new file mode 100644 index 000000000000..d3c391b16d36 --- /dev/null +++ b/Documentation/virt/kvm/arm/pvlock.rst @@ -0,0 +1,52 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Paravirtualized lock support for arm64 +====================================== + +KVM/arm64 provides a hypervisor service call for paravirtualized guests to +determine whether a VCPU is currently running or not. + +A new SMCCC compatible hypercall is defined: + +* ARM_SMCCC_VENDOR_HYP_KVM_PV_LOCK_FUNC_ID: 0xC6000002 + +ARM_SMCCC_VENDOR_HYP_KVM_PV_LOCK_FUNC_ID + + ============= ======== ========================================== + Function ID: (uint32) 0xC6000002 + Return value: (int64) IPA of the pv lock data structure for this + VCPU. On failure: + NOT_SUPPORTED (-1) + ============= ======== ========================================== + +The IPA returned by PV_LOCK_PREEMPTED should be mapped by the guest as normal +memory with inner and outer write back caching attributes, in the inner +shareable domain. + +PV_LOCK_PREEMPTED returns the structure for the calling VCPU. + +PV lock state +------------- + +The structure pointed to by the PV_LOCK_PREEMPTED hypercall is as follows: + ++-----------+-------------+-------------+---------------------------------+ +| Field | Byte Length | Byte Offset | Description | ++===========+=============+=============+=================================+ +| preempted | 8 | 0 | Indicate if the VCPU that owns | +| | | | this struct is running or not. | +| | | | Non-zero values mean the VCPU | +| | | | has been preempted. Zero means | +| | | | the VCPU is not preempted. | ++-----------+-------------+-------------+---------------------------------+ + +The preempted field will be updated to 1 by the hypervisor prior to scheduling +a VCPU. When the VCPU is scheduled out, the preempted field will be updated +to 0 by the hypervisor. + +The structure will be present within a reserved region of the normal memory +given to the guest. The guest should not attempt to write into this memory. +There is a structure per VCPU of the guest. + +For the user space interface see +:ref:`Documentation/virt/kvm/devices/vcpu.rst `. \ No newline at end of file diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst index 716aa3edae14..ea81b98f0e19 100644 --- a/Documentation/virt/kvm/devices/vcpu.rst +++ b/Documentation/virt/kvm/devices/vcpu.rst @@ -263,3 +263,28 @@ From the destination VMM process: 7. Write the KVM_VCPU_TSC_OFFSET attribute for every vCPU with the respective value derived in the previous step. + +.. _kvm_arm_vcpu_pvlock_ctrl: + +5. GROUP: KVM_ARM_VCPU_PVLOCK_CTRL +================================== + +:Architectures: ARM64 + +5.1 ATTRIBUTE: KVM_ARM_VCPU_PVLOCK_IPA +-------------------------------------- + +:Parameters: 64-bit base address + +Returns: + + ======= ====================================== + -ENXIO PV lock not implemented + -EEXIST Base address already set for this VCPU + -EINVAL Base address not 64 byte aligned + ======= ====================================== + +Specifies the base address of the pv lock structure for this VCPU. The +base address must be 64 byte aligned and exist within a valid guest memory +region. See Documentation/virt/kvm/arm/pvlock.rst for more information +including the layout of the pv lock structure.