Message ID | 20221103212125.17156-2-ansuelsmth@gmail.com |
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State | New |
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[93.42.71.18]) by smtp.googlemail.com with ESMTPSA id m29-20020a05600c3b1d00b003b47b913901sm6968320wms.1.2022.11.03.14.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 14:21:42 -0700 (PDT) From: Christian Marangi <ansuelsmth@gmail.com> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: Christian Marangi <ansuelsmth@gmail.com> Subject: [PATCH 2/2] arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table Date: Thu, 3 Nov 2022 22:21:25 +0100 Message-Id: <20221103212125.17156-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221103212125.17156-1-ansuelsmth@gmail.com> References: <20221103212125.17156-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748512364104252910?= X-GMAIL-MSGID: =?utf-8?q?1748512364104252910?= |
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[1/2] phy: qcom-qmp-pcie: split pcs_misc init cfg for ipq8074 pcs table
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Commit Message
Christian Marangi
Nov. 3, 2022, 9:21 p.m. UTC
This is not a fix on its own but more a cleanup. Phy qmp pcie driver
currently have a workaround to handle pcs_misc not declared and add
0x400 offset to the pcs reg if pcs_misc is not declared.
Correctly declare pcs_misc reg and reduce PCS size to the common value
of 0x1f0 as done for every other qmp based pcie phy device.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Comments
On 03-11-22, 22:21, Christian Marangi wrote: > This is not a fix on its own but more a cleanup. Phy qmp pcie driver > currently have a workaround to handle pcs_misc not declared and add > 0x400 offset to the pcs reg if pcs_misc is not declared. > > Correctly declare pcs_misc reg and reduce PCS size to the common value > of 0x1f0 as done for every other qmp based pcie phy device. Reviewed-by: Vinod Koul <vkoul@kernel.org>
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9ebb9e2371b1..95d7f49bc61a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -406,7 +406,8 @@ pcie_phy: phy@84000 { pcie_phy0: phy@84200 { reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ - <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ + <0x0 0x84800 0x0 0x1f0>; /* PCS: Lane0, COM, PCIE */ + <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ #phy-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>;