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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h14-20020a63df4e000000b0045cbd4e43a1si1791388pgj.57.2022.11.03.11.00.57; Thu, 03 Nov 2022 11:01:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bIWFEOAe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232081AbiKCR75 (ORCPT + 99 others); Thu, 3 Nov 2022 13:59:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232042AbiKCR71 (ORCPT ); Thu, 3 Nov 2022 13:59:27 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53C972628 for ; Thu, 3 Nov 2022 10:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498359; x=1699034359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IRafYvcGTb3XRIZ8BF10OMlvhWCpsdfukSgZuf8/1v8=; b=bIWFEOAeCGrPWyjKFHyXRC4UxDwtcJ3DglJJHuWAwJfDXrfHh9E0/wzM trifDp6L+lVtU0fBUvQ5Q7Bm3oo8D9P1ku7GM/7Dof/TFIDbcEP5hbH2a bJx26hsohmpVTRpjjlsgmpOJuX3nS6ZgnQTD94ipwORzdSsjEyi7uOSK5 D4RGpriRcl2eKseFNp7gwzunTi9DEMmJbX5mcjBE0FH2eDDr3TcKFCarr Vu33aq6MzyuvE4diI2KHzIG84wOodvOrlVbp5Pt08yB7TLE6KxxwrsE4R lV2a0xwfrJE2c11Hmyn87LlaPGd6NmvLC4ewGKnUBYjJusjTp/HY3PLUw w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476963" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476963" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762540" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762540" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:17 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 01/13] x86/microcode/intel: Prevent printing updated microcode rev multiple times Date: Thu, 3 Nov 2022 17:58:49 +0000 Message-Id: <20221103175901.164783-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498876429794153?= X-GMAIL-MSGID: =?utf-8?q?1748498876429794153?= Commit b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") introduced a race where all CPUs follow this call chain: microcode_init()->schedule_on_each_cpu(setup_online_cpu)->collect_cpu_info This results in console spam where multiple CPUs print the signature. [ 33.688639] microcode: sig=0x50654, pf=0x80, revision=0x2006e05 [ 33.688659] microcode: sig=0x50654, pf=0x80, revision=0x2006e05 [ 33.688660] microcode: sig=0x50654, pf=0x80, revision=0x2006e05 Fix by making sure only boot CPU prints the message. Fixes: b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") Reported-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 8c35c70029bf..8f7f8dd6680e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -680,6 +680,7 @@ void reload_ucode_intel(void) static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { + bool bsp = cpu_num == boot_cpu_data.cpu_index; static struct cpu_signature prev; struct cpuinfo_x86 *c = &cpu_data(cpu_num); unsigned int val[2]; @@ -696,8 +697,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) csig->rev = c->microcode; - /* No extra locking on prev, races are harmless. */ - if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) { + if (bsp && csig->rev != prev.rev) { pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n", csig->sig, csig->pf, csig->rev); prev = *csig;