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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c14-20020a170902d48e00b001729146e418si1681680plg.388.2022.11.03.11.00.57; Thu, 03 Nov 2022 11:01:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ar9go5MU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbiKCSAC (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231942AbiKCR71 (ORCPT ); Thu, 3 Nov 2022 13:59:27 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD6EC219B for ; Thu, 3 Nov 2022 10:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498359; x=1699034359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0V5W1QoeZ7jgTpO6yb+rrh5iM/UlFsilbmyJNleFWWA=; b=ar9go5MU9n8Up/U4gf0nzQpEQzOMzRgdQfWwkvQgxEdfI0JCIxnUUh+y ytyrzLsBpQhk+CpOlxZCpfnMOdfZL8rK73Q0Gw4R26s6HWEh9F5KSDbZC gZzpY6o2B9fzkNua25EucdxRVJZ3kZHYcIQZOERvCGxmQWXvdl3JHuW9I pwr7pzHShrfILTGa5AebMSqo+zoBI5jErx1o86CxaYdSNWaeX46HnPdv4 n7SVpAzbPRHnU96ILYt6wwN1JHaCeJG6dtQwZRkb1IYts+qHzXf0ZjGa1 J1J3W28yKBeiEfTFSnMcEZ0ajZMJcK5uKyg34P6sKMLIfPcYZwAexKlD8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="310878483" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="310878483" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762571" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762571" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 11/13] x86/microcode/intel: Drop wbinvd() from microcode loading Date: Thu, 3 Nov 2022 17:58:59 +0000 Message-Id: <20221103175901.164783-12-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498877093192517?= X-GMAIL-MSGID: =?utf-8?q?1748498877093192517?= Some older processors had a bad interaction when updating microcode if the caches were dirty causing machine checks. The wbinvd() was added to mitigate that before performing microcode updates. Now that Linux checks for the minimum version before performing an update, those microcode revisions can't be loaded. Remove calls to wbinvd(). Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 5d2ee76cd36c..7086670da606 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -541,11 +541,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) } old_rev = rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -776,12 +771,6 @@ static enum ucode_state apply_microcode_intel(int cpu) if (!prev_rev) prev_rev = rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);