[net-next,v4] octeon_ep: support Octeon device CNF95N
Commit Message
Add support for Octeon device CNF95N.
CNF95N is a Octeon Fusion family product with same PCI NIC
characteristics as CN93 which is currently supported by the driver.
update supported device list in Documentation.
Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
---
V3 -> V4:
- fix the lines exceeding 80 columns
V2 -> V3:
- fixed the prefix in subject: "net-next PATCH" to "PATCH net-next".
V1 -> V2:
- update supported device list in Documentation.
.../ethernet/marvell/octeon_ep.rst | 1 +
.../ethernet/marvell/octeon_ep/octep_main.c | 20 ++++++++++++++++---
.../ethernet/marvell/octeon_ep/octep_main.h | 2 ++
3 files changed, 20 insertions(+), 3 deletions(-)
base-commit: d3a4706339da26633316357efe7ab9a92ff29b2a
Comments
Hello:
This patch was applied to netdev/net-next.git (master)
by Jakub Kicinski <kuba@kernel.org>:
On Wed, 2 Nov 2022 23:05:57 -0700 you wrote:
> Add support for Octeon device CNF95N.
> CNF95N is a Octeon Fusion family product with same PCI NIC
> characteristics as CN93 which is currently supported by the driver.
>
> update supported device list in Documentation.
>
> Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
>
> [...]
Here is the summary with links:
- [net-next,v4] octeon_ep: support Octeon device CNF95N
https://git.kernel.org/netdev/net-next/c/63d9e1291484
You are awesome, thank you!
@@ -23,6 +23,7 @@ Supported Devices
=================
Currently, this driver support following devices:
* Network controller: Cavium, Inc. Device b200
+ * Network controller: Cavium, Inc. Device b400
Interface Control
=================
@@ -23,6 +23,7 @@ struct workqueue_struct *octep_wq;
/* Supported Devices */
static const struct pci_device_id octep_pci_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN93_PF)},
+ {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CNF95N_PF)},
{0, },
};
MODULE_DEVICE_TABLE(pci, octep_pci_id_tbl);
@@ -907,6 +908,18 @@ static void octep_ctrl_mbox_task(struct work_struct *work)
}
}
+static const char *octep_devid_to_str(struct octep_device *oct)
+{
+ switch (oct->chip_id) {
+ case OCTEP_PCI_DEVICE_ID_CN93_PF:
+ return "CN93XX";
+ case OCTEP_PCI_DEVICE_ID_CNF95N_PF:
+ return "CNF95N";
+ default:
+ return "Unsupported";
+ }
+}
+
/**
* octep_device_setup() - Setup Octeon Device.
*
@@ -939,9 +952,10 @@ int octep_device_setup(struct octep_device *oct)
switch (oct->chip_id) {
case OCTEP_PCI_DEVICE_ID_CN93_PF:
- dev_info(&pdev->dev,
- "Setting up OCTEON CN93XX PF PASS%d.%d\n",
- OCTEP_MAJOR_REV(oct), OCTEP_MINOR_REV(oct));
+ case OCTEP_PCI_DEVICE_ID_CNF95N_PF:
+ dev_info(&pdev->dev, "Setting up OCTEON %s PF PASS%d.%d\n",
+ octep_devid_to_str(oct), OCTEP_MAJOR_REV(oct),
+ OCTEP_MINOR_REV(oct));
octep_device_setup_cn93_pf(oct);
break;
default:
@@ -21,6 +21,8 @@
#define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200
#define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203
+#define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF
+
#define OCTEP_MAX_QUEUES 63
#define OCTEP_MAX_IQ OCTEP_MAX_QUEUES
#define OCTEP_MAX_OQ OCTEP_MAX_QUEUES