From patchwork Tue Nov 1 23:57:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13971 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3284048wru; Tue, 1 Nov 2022 16:59:26 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6QPCxC79z8i5P9CwpmtMW4laFFuNgsbQ+Mu43jjuThsH0FG1XE71GLQ/p26KFQeZPZ/W3a X-Received: by 2002:aa7:8888:0:b0:56d:41a9:dbb3 with SMTP id z8-20020aa78888000000b0056d41a9dbb3mr16880800pfe.15.1667347166250; Tue, 01 Nov 2022 16:59:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667347166; cv=none; d=google.com; s=arc-20160816; b=YrvGdKNDj8+lvGP1VpiVkWFCKpn0UX4X/aquAWjtxa3uBD99D8yF3Pz/ChfACecQVv TEbFc1vOUIQSJILN+V0GZ1JU2vRsHECvkHOf/FLZQbK4UOQ0JV66DRrPDcC+dUUYZ2DP Ny3J4l85z8OGHb9bJIrWgkwBX9pMpK+WLbPswidbbFPjrGXqunvlqrmFPwHobseVxrBh tjkbCTPV8mqMvdebzAzcMjRDRKObALatdSCVODeDZFKS6K0s9J9s4yx30BfYhSIX2vKh Z5u/IUBMKYzCVL8Wz+iRIMwa7HCAOhfXKxgcA/8esvszHdbdW30v9DOqRYOh6tWRhNHQ 4e0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mn5x54ZOs000aCU7fk27zpl1nevJ5xsmZgoD6c6JvQA=; b=0tdfaK7CfSLLVxwR0661CYGtqpKzOPWZPZafdU0SDMBS2DMw4OPWnzq743lDTp8td1 mTYxY4XO4uj8ilTwcWVo+5shv9+0gANQxu14MJyJayJoPJ01QZ9piKquQ0ZYlld9eXJA co+F1VL3kgc0p4tlbs/88JUjPdiCVmt7nHZ98n4JwKmduGkzxHSovFoRZyHnNWTyzG4l xb5Ey2DjV7qmeFZDYbyHfsYM0SO9vDUK2tn1RwpzO8HpYTln5vHjggVg89vBB2FQPdDy xAQUZrKGGbEgdHUzd1wIW8jX07PbHWgCMUHqpQVqROZUzF9XXGqGkEmr7gl5iMtkj9Gs 6qNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="PtQc/r4L"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oa2-20020a17090b1bc200b00213120e0c85si325489pjb.156.2022.11.01.16.59.12; Tue, 01 Nov 2022 16:59:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="PtQc/r4L"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230274AbiKAX6O (ORCPT + 99 others); Tue, 1 Nov 2022 19:58:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229912AbiKAX6G (ORCPT ); Tue, 1 Nov 2022 19:58:06 -0400 Received: from mail-il1-x133.google.com (mail-il1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82E6A1F9FA; Tue, 1 Nov 2022 16:57:45 -0700 (PDT) Received: by mail-il1-x133.google.com with SMTP id q5so8653536ilt.13; Tue, 01 Nov 2022 16:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mn5x54ZOs000aCU7fk27zpl1nevJ5xsmZgoD6c6JvQA=; b=PtQc/r4LykQ5tM8NKWDggoprVoNzEKDRLjMkRqPZsKd9ZUU8MfNMzdvfl5zI/ronJA FqD3T6Cnc7qSH0IDK+APVLX2/fCyd5M8zfG5Im+c/yrz3Wcuk+aXFQ+l+jr+CljTxctf yD/LzBx0zKbnmNYFc0oHHn6T6V2/nOI7BUVlW6vH1X06n0KTx7hIQvIO8GEp5gkKRHJ2 LDHNla4OtvIOawHVdFtswnhYNhIxBBaVRRmYpnPX7aH7Le2jHM8gfYCYT6ECaKqTHCJm 5qtuJoV4Hvwr1s9hsibQExgAzRKrQ/U/PD+pHuv1SxgCXgCVqnz76wEeYHca+EnY+zJV KpPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mn5x54ZOs000aCU7fk27zpl1nevJ5xsmZgoD6c6JvQA=; b=7oBN7gymlUuVhgN7MP4kT5UxIVCwtwxaqjc/U88wmqsJzhHcCIBo3fop44yrVNIVwf PNj+171ID8qERrvdjn7k6SJg0k9ZhKWTWh1ZcPo0pp/tflVc+KL2Kub74w0X0iMHM+0R UelwAubI8DC956Zcz/1Re3xEET62+T3XGDOsP+3m/74Xmh4BP4iQyAyPDZzxqLunZ53X z9tkRp43VM4JPZ3sh51HSI5GqXfdInd4deeyVqx8I3xtzH4JpHkd42fEXEtSPtlupIhu ncapahi4TENbIKur/fJi31A3zPTlrAYclDRIy1AWthy/vPz2OWbCMwWmPCxoNgRnJ3H5 8gNQ== X-Gm-Message-State: ACrzQf0EPEZqKbsGH3lxAo/A0ilG+39JLqn0exfQ+0UQhLUAwUu+tYRV OF56IbL0uCjacvcJ0MXiBeA= X-Received: by 2002:a92:ce48:0:b0:300:7d43:48ee with SMTP id a8-20020a92ce48000000b003007d4348eemr12186969ilr.314.1667347064593; Tue, 01 Nov 2022 16:57:44 -0700 (PDT) Received: from localhost ([2607:fea8:a2e2:2d00:f1f0:c4d7:e39e:e2f]) by smtp.gmail.com with ESMTPSA id o11-20020a056e02068b00b002f9f001de24sm4024960ils.21.2022.11.01.16.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 16:57:44 -0700 (PDT) From: Richard Acayan To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Robin Murphy , Chanho Park , Thierry Reding , Stephan Gerhold , Lorenzo Pieralisi , Robert Marko , Das Srinagesh , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Date: Tue, 1 Nov 2022 19:57:22 -0400 Message-Id: <20221101235722.53955-5-mailingradian@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101235722.53955-1-mailingradian@gmail.com> References: <20221101235722.53955-1-mailingradian@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748340222450821381?= X-GMAIL-MSGID: =?utf-8?q?1748340222450821381?= The Qualcomm Snapdragon 670 has been out for a while. Add a device tree for it and the Google Pixel 3a as the first device. The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work on Android 10 bootloaders or later until it gets fixed for the Pixel 3. SoC Initial Features: - power management - clocks - pinctrl - eMMC - USB 2.0 - GENI I2C - IOMMU - RPMh - interrupts Device-Specific Initial Features: - side buttons (keys) - regulators - touchscreen Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++ arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++ 3 files changed, 1736 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..4eb5d8829efb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts new file mode 100644 index 000000000000..fa3dee78e442 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Google Pixel 3a, adapted from google-blueline device tree, + * xiaomi-lavender device tree, and oneplus-common device tree. + * + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sdm670.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &adsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + model = "Google Pixel 3a"; + compatible = "google,sargo", "qcom,sdm670"; + qcom,board-id = <0x00041e05 0>; + qcom,msm-id = <321 0x20001>; + + aliases { }; + + chosen { + stdout-path = "serial0:115200n8"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>; + width = <1080>; + height = <2220>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + mpss_region: mpss@8b000000 { + reg = <0 0x8b000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@94800000 { + reg = <0 0x94800000 0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@94d00000 { + reg = <0 0x94d00000 0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@94e00000 { + reg = <0 0x94e00000 0 0x800000>; + no-map; + }; + + mba_region: mba@95600000 { + reg = <0 0x95600000 0 0x200000>; + no-map; + }; + + adsp_mem: adsp@95800000 { + reg = <0 0x95800000 0 0x2200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@97a00000 { + reg = <0 0x97a00000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@97a10000 { + reg = <0 0x97a10000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97a15000 { + reg = <0 0x97a15000 0 0x2000>; + no-map; + }; + + framebuffer-region@9c000000 { + reg = <0 0x9c000000 0 0x2400000>; + no-map; + }; + + /* Also includes ramoops regions */ + debug_info_mem: debug-info@a1800000 { + reg = <0 0xa1800000 0 0x411000>; + no-map; + }; + }; + + /* + * Supply map from xiaomi-lavender specifies this as the supply for + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies + * this as a power domain. Set this as a fixed regulator with the same + * voltage as lavender until display is needed to avoid unneccessarily + * using a deprecated binding (regulator-fixed-domain). + */ + vreg_s2b_1p05: vreg-s2b-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin>; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + }; + }; + + /* + * The touchscreen regulator seems to be controlled somehow by a gpio. + * Model it as a fixed regulator and keep it on. Without schematics we + * don't know how this is actually wired up... + */ + ts_1p8_supply: ts-1p8-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_1p8_supply"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&apps_rsc { + pm660l-regulators { + compatible = "qcom,pm660l-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>; + vdd-l2-supply = <&vreg_bob>; + vdd-l3-l5-l7-l8-supply = <&vreg_bob>; + vdd-l4-l6-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + /* LDOs */ + vreg_l1b_0p89: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2b_2p38: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3b_2p93: ldo3 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3008000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l4b_2p96: ldo4 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5b_2p96: ldo5 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6b_3p15: ldo6 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7b_3p1: ldo7 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + + /* + * Downstream specifies a fixed voltage of 3.312 V, but the + * PMIC4 BOB ranges don't support that. Widen the range a + * little to avoid adding a new BOB regulator type. + */ + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <500>; + }; + }; + + pm660-regulators { + compatible = "qcom,pm660-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l1-l6-l7-supply = <&vreg_s6a_1p29>; + vdd-l2-l3-supply = <&vreg_s2b_1p05>; + vdd-l5-supply = <&vreg_s2b_1p05>; + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_1p92>; + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_1p92: smps4 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_1p29: smps6 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p28: ldo6 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: ldo7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_2p38: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l17a_2p38: ldo17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + }; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + clock-frequency = <100000>; + + synaptics-rmi4-i2c@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <0x1>; + #size-cells = <0x0>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + + /* VDD supply isn't specified, bind it to power */ + vdd-supply = <&vph_pwr>; + vio-supply = <&ts_1p8_supply>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + touchscreen-x-mm = <62>; + touchscreen-y-mm = <127>; + syna,sensor-type = <1>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + ; +}; + +&pm660l_gpios { + vol_up_pin: vol-up-state { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = ; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + +&sdhc_1 { + status = "okay"; + supports-cqe; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + + qcom,ddr-config = <0xc3040873>; + + vmmc-supply = <&vreg_l4b_2p96>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + touchscreen_default: ts-default-state { + ts-reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + + ts-irq-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts-switch-pins { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p89>; + vdda-pll-supply = <&vreg_l10a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p1>; +}; + +&usb_1 { + status = "okay"; + + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + /* Only peripheral works for now */ + dr_mode = "peripheral"; + + /* Do not assume that sdm670.dtsi will never support USB 3.0 */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi new file mode 100644 index 000000000000..4450ece839a0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -0,0 +1,1216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { }; + + chosen { }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-mem@85700000 { + reg = <0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: xbl-mem@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: aop-mem@85fc0000 { + reg = <0 0x85fc0000 0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85fe0000 0 0x20000>; + no-map; + }; + + camera_mem: camera-mem@8ab00000 { + reg = <0 0x8ab00000 0 0x500000>; + no-map; + }; + + mpss_region: mpss@8b000000 { + reg = <0 0x8b000000 0 0x7e00000>; + no-map; + }; + + venus_mem: venus@92e00000 { + reg = <0 0x92e00000 0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@93300000 { + reg = <0 0x93300000 0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@93400000 { + reg = <0 0x93400000 0 0x800000>; + no-map; + }; + + mba_region: mba@93c00000 { + reg = <0 0x93c00000 0 0x200000>; + no-map; + }; + + adsp_mem: adsp@93e00000 { + reg = <0 0x93e00000 0 0x1e00000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@95c00000 { + reg = <0 0x95c00000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@95c10000 { + reg = <0 0x95c10000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@95c15000 { + reg = <0 0x95c15000 0 0x2000>; + no-map; + }; + + spss_mem: spss@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; + + qseecom_mem: qseecom@9e400000 { + reg = <0 0x9e400000 0 0x1400000>; + no-map; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x600>; + enable-method = "psci"; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x700>; + enable-method = "psci"; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <1617>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <2380>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9825>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdm670", "qcom,scm"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm670"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7c4000 { + compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>, + <0 0x007c8000 0 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + clock-names = "iface", "core", "xo", "ice", "bus"; + + iommus = <&apps_smmu 0x140 0xf>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + power-domains = <&rpmhpd SDM670_CX>; + + bus-width = <8>; + non-removable; + + status = "disabled"; + }; + + gpi_dma0: dma-controller@800000 { + #dma-cells = <3>; + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x0016 0x0>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + #dma-cells = <3>; + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x06d6 0x0>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x6c3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + tlmm: pinctrl@3400000 { + compatible = "qcom,sdm670-tlmm"; + reg = <0 0x03400000 0 0xc00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio17", "gpio18"; + function = "qup1"; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio27", "gpio28"; + function = "qup2"; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio41", "gpio42"; + function = "qup3"; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio89", "gpio90"; + function = "qup4"; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio85", "gpio86"; + function = "qup5"; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio45", "gpio46"; + function = "qup6"; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio93", "gpio94"; + function = "qup7"; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio65", "gpio66"; + function = "qup8"; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio55", "gpio56"; + function = "qup10"; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio31", "gpio32"; + function = "qup11"; + }; + + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio49", "gpio50"; + function = "qup12"; + }; + + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio105", "gpio106"; + function = "qup13"; + }; + + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio33", "gpio34"; + function = "qup14"; + }; + + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio81", "gpio82"; + function = "qup15"; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + }; + + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; + reg = <0 0x088e2000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + }; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + apps_smmu: iommu@15000000 { + /* + * The hardware tolerates the SDM845 reset quirk. The + * iommu maintainers aren't responding to any patches + * that would add support for new platforms. Set this + * compatible so this dtsi is valid and functional. + */ + compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_rsc: rsc@179c0000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0 0x179c0000 0 0x10000>, + <0 0x179d0000 0 0x10000>, + <0 0x179e0000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdm670-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sdm670-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0x17a00000 0 0x10000>, /* GICD */ + <0 0x17a60000 0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + }; +};