From patchwork Tue Nov 1 09:01:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 13568 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2832585wru; Tue, 1 Nov 2022 02:05:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM71TUuwoyhkP2oNF4o77jPkFhkAJ/UJqU99ddyg/HlBXwZWFYtmpbARiGc9KhHLrIWtfssX X-Received: by 2002:a17:907:a05:b0:77b:b538:6476 with SMTP id bb5-20020a1709070a0500b0077bb5386476mr17395320ejc.324.1667293548534; Tue, 01 Nov 2022 02:05:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667293548; cv=none; d=google.com; s=arc-20160816; b=s4yZ57O7xOdADrPZVg2KDdulloldV4jNSeErgch1yzARqMeROhFBcDo9u8OhPGA5Ua Cv9wUQLUcmZWGfbnRPHRb5W7O3n1/bsX8cZ33qkW0DjQiOHPBHEVBRC+4BivbZ7W5nkq nVo8Hpn6fMpgjxywmXyFhTISO303FKqk9S66FjhDyp5btqo5KcNxS1Sd8UoQhdaTLxXm L7dnAa0okRlefmc26XSxfz0s7O5oSDQ0DF6omzKBokKbUYBOMcW92RVycDpq1fOmrD+7 RdpWdq0B+jiZt9b1ts/BAgrBKc7/w/SQbta9r1PzFcp0uj42kvJ55fpB6PThVVsTuvvq yJMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=yZwbGytlV0jCEQ5lq60t537MK1vaJzD7e28M+0BYoBw=; b=sTHWYVWM2R2Ljtp4RJkxhMBNEGMNPwWSr+6aXAwutupcgLtf3706IQ+a27dtdJ4ixC qzZ7sptuhfHVSZulsLr8BUvHN+QRmboKkFbkJJ8Bz5HDEWLq4t60ZJDusgYBIHjnDHvu +ECgvsTUy/iFksZwUvppWmsIQe7pQDDDj0L/xAEo5TgrkaEW1ZS/KicFGje2Hrf+tm94 skHFyle7zwDezzLqe7sFtSlfSC00hJQwQ6hVWgXE3V5pJaIyxWOW/P1mt1rQGdq4WDBC fupXKrDwua+PApP9hQOAjBcXxvg2/wyoQMKHSMhfY0K5zwL1iXx7lLfQB1LDhCLB9YZn kWPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=G0LdQhoa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id my15-20020a1709065a4f00b007879808e995si8764293ejc.55.2022.11.01.02.05.12; Tue, 01 Nov 2022 02:05:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=G0LdQhoa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229946AbiKAJCT (ORCPT + 99 others); Tue, 1 Nov 2022 05:02:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229982AbiKAJBs (ORCPT ); Tue, 1 Nov 2022 05:01:48 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B2FD186F6; Tue, 1 Nov 2022 02:01:42 -0700 (PDT) X-UUID: 4463ce1501c44bb2894eabe1e9536d5a-20221101 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yZwbGytlV0jCEQ5lq60t537MK1vaJzD7e28M+0BYoBw=; b=G0LdQhoa0JMCIZjHXEuGR1atEPSiIpdsfOWWOdJiBKdRpvwNj7tYED5FqQ6vVPI/lDRLNPXTE6rPnyeXC8u9SyNijXqvRpjm33CNiGoNY6DWUNRa0grkh3sD24xuxM3T4lUiMn2q4V5ncyxu1AB8z+fwFwY102KqzRkMiK22a/g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:3952d48a-8c3c-4ae2-959f-3d39535fca8a,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:62cd327,CLOUDID:24273b90-1a78-4832-bd08-74b1519dcfbf,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 4463ce1501c44bb2894eabe1e9536d5a-20221101 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 846228101; Tue, 01 Nov 2022 17:01:32 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 1 Nov 2022 17:01:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 1 Nov 2022 17:01:32 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , "Matthias Brugger" , Rob Herring CC: , , , , , , , , Allen-KH Cheng Subject: [PATCH v3 5/7] dt-bindings: watchdog: mediatek: Convert mtk-wdt to json-schema Date: Tue, 1 Nov 2022 17:01:14 +0800 Message-ID: <20221101090116.27130-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221101090116.27130-1-allen-kh.cheng@mediatek.com> References: <20221101090116.27130-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748283999589456606?= X-GMAIL-MSGID: =?utf-8?q?1748283999589456606?= From: AngeloGioacchino Del Regno Convert the MediaTek watchdog bindings to schema. The original binding only had 4 without a fallback but there is a reset controller on the "mediatek,mt7986-wdt", "mediatek,mt8186-wdt", "mediatek,mt8188-wdt" and "mediatek,mt8195-wdt" Since there is no reset controller for the mt6589, we remove "mediatek,mt6589-wdt" as a fallback. Signed-off-by: AngeloGioacchino Del Regno Co-developed-by: Allen-KH Cheng Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck Reviewed-by: Nícolas F. R. A. Prado --- .../bindings/watchdog/mediatek,mtk-wdt.yaml | 78 +++++++++++++++++++ .../devicetree/bindings/watchdog/mtk-wdt.txt | 43 ---------- 2 files changed, 78 insertions(+), 43 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml delete mode 100644 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml new file mode 100644 index 000000000000..b0d71fa28ac3 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoCs Watchdog timer + +maintainers: + - Matthias Brugger + +description: + The watchdog supports a pre-timeout interrupt that fires + timeout-sec/2 before the expiry. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-wdt + - mediatek,mt6589-wdt + - mediatek,mt7986-wdt + - mediatek,mt8183-wdt + - mediatek,mt8186-wdt + - mediatek,mt8188-wdt + - mediatek,mt8192-wdt + - mediatek,mt8195-wdt + - items: + - enum: + - mediatek,mt2701-wdt + - mediatek,mt6582-wdt + - mediatek,mt6797-wdt + - mediatek,mt7622-wdt + - mediatek,mt7623-wdt + - mediatek,mt7629-wdt + - mediatek,mt8516-wdt + - const: mediatek,mt6589-wdt + + reg: + maxItems: 1 + + interrupts: + items: + - description: Watchdog pre-timeout (bark) interrupt + + mediatek,disable-extrst: + description: Disable sending output reset signal + type: boolean + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt"; + reg = <0 0x10007000 0 0x100>; + interrupts = ; + mediatek,disable-extrst; + timeout-sec = <10>; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt deleted file mode 100644 index b900c85d4560..000000000000 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ /dev/null @@ -1,43 +0,0 @@ -Mediatek SoCs Watchdog timer - -The watchdog supports a pre-timeout interrupt that fires timeout-sec/2 -before the expiry. - -Required properties: - -- compatible should contain: - "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 - "mediatek,mt2712-wdt": for MT2712 - "mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582 - "mediatek,mt6589-wdt": for MT6589 - "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 - "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 - "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 - "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 - "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986 - "mediatek,mt8183-wdt": for MT8183 - "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186 - "mediatek,mt8188-wdt", "mediatek,mt6589-wdt": for MT8188 - "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 - "mediatek,mt8192-wdt": for MT8192 - "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195 - -- reg : Specifies base physical address and size of the registers. - -Optional properties: -- mediatek,disable-extrst: disable send output reset signal -- interrupts: Watchdog pre-timeout (bark) interrupt. -- timeout-sec: contains the watchdog timeout in seconds. -- #reset-cells: Should be 1. - -Example: - -watchdog: watchdog@10007000 { - compatible = "mediatek,mt8183-wdt", - "mediatek,mt6589-wdt"; - mediatek,disable-extrst; - reg = <0 0x10007000 0 0x100>; - interrupts = ; - timeout-sec = <10>; - #reset-cells = <1>; -};