diff mbox series

[16/20] arm64: dts: Update cache properties for realtek

Message ID	20221031092057.533368-1-pierre.gondois@arm.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Pierre Gondois <pierre.gondois@arm.com> To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, =?utf-8?q?Andreas_F=C3=A4rb?= =?utf-8?q?er?= <afaerber@suse.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 16/20] arm64: dts: Update cache properties for realtek Date: Mon, 31 Oct 2022 10:20:57 +0100 Message-Id: <20221031092057.533368-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Update cache properties for arm64 DTS \| [00/20] Update cache properties for arm64 DTS [01/20] arm64: dts: Update cache properties for amd [02/20] arm64: dts: Update cache properties for amlogic [03/20] arm64: dts: Update cache properties for apm [04/20] arm64: dts: Update cache properties for arm [05/20] arm64: dts: Update cache properties for broadcom [06/20] arm64: dts: Update cache properties for exynos [07/20] arm64: dts: Update cache properties for freescale [08/20] arm64: dts: Update cache properties for hisilicon [09/20] arm64: dts: Update cache properties for lg [10/20] arm64: dts: Update cache properties for marvell [11/20] arm64: dts: Update cache properties for mediatek [12/20] arm64: dts: Update cache properties for microchip [13/20] arm64: dts: Update cache properties for nuvoton [14/20] arm64: dts: Update cache properties for nvidia [15/20] arm64: dts: Update cache properties for qcom [16/20] arm64: dts: Update cache properties for realtek [17/20] arm64: dts: Update cache properties for renesas [18/20] arm64: dts: Update cache properties for rockchip [19/20] arm64: dts: Update cache properties for synaptics [20/20] arm64: dts: Update cache properties for tesla

Commit Message

Pierre Gondois Oct. 31, 2022, 9:20 a.m. UTC

  The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes

The recently added init_of_cache_level() function checks
these properties. Add them if missing.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
 arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
 arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
 arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
 arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
 arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
 5 files changed, 6 insertions(+)

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
index 2d92b56ac94d..0696b99fc40d 100644
--- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
@@ -30,6 +30,7 @@  cpu1: cpu@1 {
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
index 1402abe80ea1..4ca322e420e6 100644
--- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
@@ -44,6 +44,7 @@  cpu3: cpu@3 {
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
index fb864a139c97..03fccd48f0c0 100644
--- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
@@ -44,6 +44,7 @@  cpu3: cpu@3 {
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
index 05c9216a87ee..94c0a8cf4953 100644
--- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
@@ -44,6 +44,7 @@  cpu3: cpu@3 {
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
index afba5f04c8ec..2ee9ba1ecdc1 100644
--- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
@@ -87,12 +87,14 @@  cpu5: cpu@500 {
 
 		l2: l2-cache {
 			compatible = "cache";
+			cache-level = <2>;
 			next-level-cache = <&l3>;
 
 		};
 
 		l3: l3-cache {
 			compatible = "cache";
+			cache-level = <3>;
 		};
 	};