[12/20] arm64: dts: Update cache properties for microchip

Message ID 20221031092030.533116-1-pierre.gondois@arm.com
State New
Headers
Series Update cache properties for arm64 DTS |

Commit Message

Pierre Gondois Oct. 31, 2022, 9:20 a.m. UTC
  The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes

The recently added init_of_cache_level() function checks
these properties. Add them if missing.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
 arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
 1 file changed, 1 insertion(+)
  

Patch

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2dd5e38820b1..c4bca23b96b9 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -52,6 +52,7 @@  cpu1: cpu@1 {
 		};
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};