From patchwork Sat Oct 29 14:16:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 12714 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1370361wru; Sat, 29 Oct 2022 07:18:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6X+8NIVRnoQtTxzXiLszFaFq/F84SfXvr77jYV0eBen732KTkS4KxnZ1qCwK0eby8f58O5 X-Received: by 2002:a17:90a:a087:b0:213:ba17:2c8c with SMTP id r7-20020a17090aa08700b00213ba172c8cmr1486911pjp.80.1667053090071; Sat, 29 Oct 2022 07:18:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667053090; cv=none; d=google.com; s=arc-20160816; b=wYwOAVAq8coAiPuCsvXW/4+vebOuv9xSuQRysnXAqAeJ+ldW7y/FngZXjriJ+NeZzD v2AdnxUvDTXBUZaRar7/i4NGc5Cp71kfyNjIif/xImIXLAjOS9Lo9MfcCy4mwxSREyoi PovGYYsaDknREZ4D/J+8FsYMw/M+XOtR7KNGMdkKDtQajHOPI7ANq4K1n2CzYQGWye4F e8ANfZfQQaT9umR7M7yfhHcUapAoFppeSV/oS4Yj1kqIMq/mWGdowjST+mt7ukskrQPS Ya+r6OGyVTwfIEGAl1RLn4plaGdT0IPZmuiixDqsECo7AIvt8cSseNI6idXzBxgeBCBV a0jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UOoqLNyuuMkjbVp19mgUKWvRIJvnsAjwJ6O0U+9uTpw=; b=CuxLHhoFutCgVp7evDLgimMHV3bfXzRcTNkYvX5l5DuApdDVuY0ANwUL5A0o0hMjge HDSuZe6PJEYKJt73b50WiCf2r28AXttM3G5ZWHklh295rMaQPDMG6lF4vkUX7ljS+gmc 2fmKvbCq90ug+w4LkGyb3Rv7RdZDGQ7o5gZX7EEfweHGK4r5EivhQ8Lovs57a+aSuhS1 ezrUMmc84EcRHFSblo6Q7Hde0DkWggqAyAqXNxXruNm1JAgwsA7tJcyHqB3GSyPSr0YF AjDuoyiWptKMP9Kh0zIp05sBkxpsfoWhr1L+qZ8bkGNu9jQ5QlJ7vNuOSFt2c55P/ZRS C3Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ICH8XE7I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lx18-20020a17090b4b1200b002131d14d06dsi2306370pjb.159.2022.10.29.07.17.57; Sat, 29 Oct 2022 07:18:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ICH8XE7I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229950AbiJ2ORd (ORCPT + 99 others); Sat, 29 Oct 2022 10:17:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229838AbiJ2ORX (ORCPT ); Sat, 29 Oct 2022 10:17:23 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC6D35F225 for ; Sat, 29 Oct 2022 07:17:05 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id 4so7237420pli.0 for ; Sat, 29 Oct 2022 07:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UOoqLNyuuMkjbVp19mgUKWvRIJvnsAjwJ6O0U+9uTpw=; b=ICH8XE7IolrkK90QN6h5QPb0d8tTu4Uy5l3YJd81dVI4zUssLBF2g5kgde7B6jfmzF 71LlzQeo2eel7ShBATOKHuEYBbyF7CiYlYgXcI2RLc7MV+WGjaHdcCy41DjzpQuhSTIS fQCNAipSZIuz/mFWgA5e00eV7Vku5M9jqf5bjcKFgy6kpKHd5Yx/h2cOxM+PrPYoTaXv iaDc1j19+2hgz76cNKwRtE1cmUH3osxrKBaWhZbaYLI88CiPPAaYUdWkr5hnlMQ5Dqi8 I1/e1Nrsfa4Wu8ewANSoK7zesnOfcowccKyX1MzVjHm4jTyFnE/wnJDDVW6CcMWAlz+B M1gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UOoqLNyuuMkjbVp19mgUKWvRIJvnsAjwJ6O0U+9uTpw=; b=3ZkNFh0EvzerLHKdbWQPgB2XsL5ryQ+cfSq1B4vw30qynEmicvuh8Zl4C2B+XtrdG0 zkqrmYepcUhpukxr1tBy9No4ouLdqLxImRYcCZNLK6UzfviR+BiYdnmILq5IZPnCDdIo JpEKz/4qoz4pTlzRhSU8Rni7RZqLQrsOVAgLHjAycldgU4Fay8bh4h0RJZehbXB/TYDX 137uaQKNeGKCZKpvc07Kj70jdnv8kCeyh9tF7gjUYEzC+P7K6dD5JTAKxQC9k69tayvc iFEZAEIfZ5b+55a74+zHr2oRG3Q4ENHFoCxDVBZkWVTb844R6Q2IoZ6fmhZCxhUaxr9u hbjw== X-Gm-Message-State: ACrzQf2v5cRUv8z39C5efOIbp5lwL7N+hGSgy1+TrFrxNqzIbYqQmVYH JtZe1j+buVk5f/1DtlceShJs X-Received: by 2002:a17:902:7b91:b0:185:4548:3a96 with SMTP id w17-20020a1709027b9100b0018545483a96mr4556233pll.130.1667053025451; Sat, 29 Oct 2022 07:17:05 -0700 (PDT) Received: from localhost.localdomain ([117.193.208.18]) by smtp.gmail.com with ESMTPSA id u4-20020a170902e5c400b001866049ddb1sm1370157plf.161.2022.10.29.07.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Oct 2022 07:17:04 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 04/15] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Date: Sat, 29 Oct 2022 19:46:22 +0530 Message-Id: <20221029141633.295650-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221029141633.295650-1-manivannan.sadhasivam@linaro.org> References: <20221029141633.295650-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748031860833126262?= X-GMAIL-MSGID: =?utf-8?q?1748031860833126262?= UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of SM8150. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 68 ++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 5f2a012707b7..fa7457c0202b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -385,6 +385,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -420,7 +424,32 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), +}; +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), }; static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { @@ -433,6 +462,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -774,6 +808,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .phy_status = PHYSTATUS, }; +static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { + .lanes = 2, + + .tables = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sm8150_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), + .rx = sm8150_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs = sm8150_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tables_hs_g4 = { + .tx = sm8250_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx = sm8250_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs = sm8250_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_pcs), + }, + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .lanes = 2, @@ -1226,7 +1292,7 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { .data = &sm8150_ufsphy_cfg, }, { .compatible = "qcom,sm8250-qmp-ufs-phy", - .data = &sm8150_ufsphy_cfg, + .data = &sm8250_ufsphy_cfg, }, { .compatible = "qcom,sm8350-qmp-ufs-phy", .data = &sm8350_ufsphy_cfg,