[v2,4/4] rtc: jz4740: Support for fine-tuning the RTC clock
Commit Message
Write the NC1HZ and ADJC register fields, which allow to tweak the
frequency of the RTC clock, so that it can run as accurately as
possible.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/rtc/rtc-jz4740.c | 45 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
Comments
Hi Paul,
I love your patch! Yet something to improve:
[auto build test ERROR on abelloni/rtc-next]
[also build test ERROR on robh/for-next linus/master v6.1-rc2 next-20221028]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Paul-Cercueil/rtc-ingenic-various-updates/20221029-065805
base: https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-next
patch link: https://lore.kernel.org/r/20221028225519.89210-5-paul%40crapouillou.net
patch subject: [PATCH v2 4/4] rtc: jz4740: Support for fine-tuning the RTC clock
config: sparc64-randconfig-c043-20221028
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/b73614c39710acaff7977b8d3ec935105cf59757
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Paul-Cercueil/rtc-ingenic-various-updates/20221029-065805
git checkout b73614c39710acaff7977b8d3ec935105cf59757
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sparc64 SHELL=/bin/bash drivers/rtc/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from <command-line>:
drivers/rtc/rtc-jz4740.c: In function 'jz4740_rtc_set_offset':
>> include/linux/compiler_types.h:357:45: error: call to '__compiletime_assert_248' declared with attribute error: FIELD_PREP: value too large for the field
357 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^
include/linux/compiler_types.h:338:25: note: in definition of macro '__compiletime_assert'
338 | prefix ## suffix(); \
| ^~~~~~
include/linux/compiler_types.h:357:9: note: in expansion of macro '_compiletime_assert'
357 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:68:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
68 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:114:17: note: in expansion of macro '__BF_FIELD_CHECK'
114 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/rtc/rtc-jz4740.c:256:17: note: in expansion of macro 'FIELD_PREP'
256 | nc1hz = FIELD_PREP(JZ_RTC_REGULATOR_NC1HZ_MASK, nc1hz);
| ^~~~~~~~~~
vim +/__compiletime_assert_248 +357 include/linux/compiler_types.h
eb5c2d4b45e3d2 Will Deacon 2020-07-21 343
eb5c2d4b45e3d2 Will Deacon 2020-07-21 344 #define _compiletime_assert(condition, msg, prefix, suffix) \
eb5c2d4b45e3d2 Will Deacon 2020-07-21 345 __compiletime_assert(condition, msg, prefix, suffix)
eb5c2d4b45e3d2 Will Deacon 2020-07-21 346
eb5c2d4b45e3d2 Will Deacon 2020-07-21 347 /**
eb5c2d4b45e3d2 Will Deacon 2020-07-21 348 * compiletime_assert - break build and emit msg if condition is false
eb5c2d4b45e3d2 Will Deacon 2020-07-21 349 * @condition: a compile-time constant condition to check
eb5c2d4b45e3d2 Will Deacon 2020-07-21 350 * @msg: a message to emit if condition is false
eb5c2d4b45e3d2 Will Deacon 2020-07-21 351 *
eb5c2d4b45e3d2 Will Deacon 2020-07-21 352 * In tradition of POSIX assert, this macro will break the build if the
eb5c2d4b45e3d2 Will Deacon 2020-07-21 353 * supplied condition is *false*, emitting the supplied error message if the
eb5c2d4b45e3d2 Will Deacon 2020-07-21 354 * compiler has support to do so.
eb5c2d4b45e3d2 Will Deacon 2020-07-21 355 */
eb5c2d4b45e3d2 Will Deacon 2020-07-21 356 #define compiletime_assert(condition, msg) \
eb5c2d4b45e3d2 Will Deacon 2020-07-21 @357 _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
eb5c2d4b45e3d2 Will Deacon 2020-07-21 358
Hi Bot,
Well this report is on my RFC patch so I consider the patchset to still
be valid.
If I can actually test my RFC patch I'll send it again with this bug
fixed.
Cheers,
-Paul
Le sam. 29 oct. 2022 à 16:51:53 +0800, kernel test robot
<lkp@intel.com> a écrit :
> Hi Paul,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on abelloni/rtc-next]
> [also build test ERROR on robh/for-next linus/master v6.1-rc2
> next-20221028]
> [If your patch is applied to the wrong git tree, kindly drop us a
> note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url:
> https://github.com/intel-lab-lkp/linux/commits/Paul-Cercueil/rtc-ingenic-various-updates/20221029-065805
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git
> rtc-next
> patch link:
> https://lore.kernel.org/r/20221028225519.89210-5-paul%40crapouillou.net
> patch subject: [PATCH v2 4/4] rtc: jz4740: Support for fine-tuning
> the RTC clock
> config: sparc64-randconfig-c043-20221028
> compiler: sparc64-linux-gcc (GCC) 12.1.0
> reproduce (this is a W=1 build):
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> #
> https://github.com/intel-lab-lkp/linux/commit/b73614c39710acaff7977b8d3ec935105cf59757
> git remote add linux-review
> https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review
> Paul-Cercueil/rtc-ingenic-various-updates/20221029-065805
> git checkout b73614c39710acaff7977b8d3ec935105cf59757
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0
> make.cross W=1 O=build_dir ARCH=sparc64 SHELL=/bin/bash drivers/rtc/
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> In file included from <command-line>:
> drivers/rtc/rtc-jz4740.c: In function 'jz4740_rtc_set_offset':
>>> include/linux/compiler_types.h:357:45: error: call to
>>> '__compiletime_assert_248' declared with attribute error:
>>> FIELD_PREP: value too large for the field
> 357 | _compiletime_assert(condition, msg,
> __compiletime_assert_, __COUNTER__)
> | ^
> include/linux/compiler_types.h:338:25: note: in definition of
> macro '__compiletime_assert'
> 338 | prefix ## suffix();
> \
> | ^~~~~~
> include/linux/compiler_types.h:357:9: note: in expansion of macro
> '_compiletime_assert'
> 357 | _compiletime_assert(condition, msg,
> __compiletime_assert_, __COUNTER__)
> | ^~~~~~~~~~~~~~~~~~~
> include/linux/build_bug.h:39:37: note: in expansion of macro
> 'compiletime_assert'
> 39 | #define BUILD_BUG_ON_MSG(cond, msg)
> compiletime_assert(!(cond), msg)
> | ^~~~~~~~~~~~~~~~~~
> include/linux/bitfield.h:68:17: note: in expansion of macro
> 'BUILD_BUG_ON_MSG'
> 68 |
> BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
> | ^~~~~~~~~~~~~~~~
> include/linux/bitfield.h:114:17: note: in expansion of macro
> '__BF_FIELD_CHECK'
> 114 | __BF_FIELD_CHECK(_mask, 0ULL, _val,
> "FIELD_PREP: "); \
> | ^~~~~~~~~~~~~~~~
> drivers/rtc/rtc-jz4740.c:256:17: note: in expansion of macro
> 'FIELD_PREP'
> 256 | nc1hz = FIELD_PREP(JZ_RTC_REGULATOR_NC1HZ_MASK,
> nc1hz);
> | ^~~~~~~~~~
>
>
> vim +/__compiletime_assert_248 +357 include/linux/compiler_types.h
>
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 343
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 344 #define
> _compiletime_assert(condition, msg, prefix, suffix) \
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 345
> __compiletime_assert(condition, msg, prefix, suffix)
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 346
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 347 /**
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 348 * compiletime_assert -
> break build and emit msg if condition is false
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 349 * @condition: a
> compile-time constant condition to check
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 350 * @msg: a message
> to emit if condition is false
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 351 *
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 352 * In tradition of POSIX
> assert, this macro will break the build if the
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 353 * supplied condition is
> *false*, emitting the supplied error message if the
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 354 * compiler has support
> to do so.
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 355 */
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 356 #define
> compiletime_assert(condition, msg) \
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 @357
> _compiletime_assert(condition, msg, __compiletime_assert_,
> __COUNTER__)
> eb5c2d4b45e3d2 Will Deacon 2020-07-21 358
>
> --
> 0-DAY CI Kernel Test Service
> https://01.org/lkp
@@ -5,6 +5,7 @@
* JZ4740 SoC RTC driver
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
@@ -41,6 +42,9 @@
#define JZ_RTC_CTRL_AE BIT(2)
#define JZ_RTC_CTRL_ENABLE BIT(0)
+#define JZ_RTC_REGULATOR_NC1HZ_MASK GENMASK(15, 0)
+#define JZ_RTC_REGULATOR_ADJC_MASK GENMASK(25, 16)
+
/* Magic value to enable writes on jz4780 */
#define JZ_RTC_WENR_MAGIC 0xA55A
@@ -61,6 +65,7 @@ struct jz4740_rtc {
enum jz4740_rtc_type type;
struct rtc_device *rtc;
+ struct clk *clk;
struct clk_hw clk32k;
@@ -217,12 +222,51 @@ static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
}
+static int jz4740_rtc_read_offset(struct device *dev, long *offset)
+{
+ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+ long rate = clk_get_rate(rtc->clk);
+ s32 nc1hz, adjc, offset1k;
+ u32 reg;
+
+ reg = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_REGULATOR);
+ nc1hz = FIELD_GET(JZ_RTC_REGULATOR_NC1HZ_MASK, reg);
+ adjc = FIELD_GET(JZ_RTC_REGULATOR_ADJC_MASK, reg);
+
+ offset1k = (nc1hz - rate + 1) * 1024L + adjc;
+ *offset = offset1k * 1000000L / (rate * 1024L);
+
+ return 0;
+}
+
+static int jz4740_rtc_set_offset(struct device *dev, long offset)
+{
+ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+ long rate = clk_get_rate(rtc->clk);
+ s32 offset1k, adjc, nc1hz;
+
+ offset1k = div_s64_rem(offset * rate * 1024LL, 1000000LL, &adjc);
+ nc1hz = rate - 1 + offset1k / 1024L;
+
+ if (adjc < 0) {
+ nc1hz--;
+ adjc += 1024;
+ }
+
+ nc1hz = FIELD_PREP(JZ_RTC_REGULATOR_NC1HZ_MASK, nc1hz);
+ adjc = FIELD_PREP(JZ_RTC_REGULATOR_ADJC_MASK, adjc);
+
+ return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, nc1hz | adjc);
+}
+
static const struct rtc_class_ops jz4740_rtc_ops = {
.read_time = jz4740_rtc_read_time,
.set_time = jz4740_rtc_set_time,
.read_alarm = jz4740_rtc_read_alarm,
.set_alarm = jz4740_rtc_set_alarm,
.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
+ .read_offset = jz4740_rtc_read_offset,
+ .set_offset = jz4740_rtc_set_offset,
};
static irqreturn_t jz4740_rtc_irq(int irq, void *data)
@@ -353,6 +397,7 @@ static int jz4740_rtc_probe(struct platform_device *pdev)
spin_lock_init(&rtc->lock);
+ rtc->clk = clk;
platform_set_drvdata(pdev, rtc);
device_init_wakeup(dev, 1);