From patchwork Fri Oct 28 13:14:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 12263 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp819033wru; Fri, 28 Oct 2022 06:07:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6WccR8ALXeZYxBnX6KcxN2xjsPuj93N6ynmWVNi2B7Fv5odOEhBXaPI4UfSqBNzy/Fqev6 X-Received: by 2002:aa7:de81:0:b0:461:2122:a807 with SMTP id j1-20020aa7de81000000b004612122a807mr39806560edv.382.1666962430664; Fri, 28 Oct 2022 06:07:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666962430; cv=none; d=google.com; s=arc-20160816; b=XSrvmV4ww+24AQ/h2dVGLDPofpfgAWuKnpIIEM//kYIXJzry6mn0j8l1cWyARZF+W1 edNt8yHz/drDvSKPveqztXL1B70t4nUHobnkkBHzjS/FaTjZlHV9d6dY3UREEi4i8vNi t0ySsow+iKEBVg2FJjaulibDd1aI9f0PQiORiWqIU4oG20DmvXs/w88F7v73mvTCOaHM uXHXQyvlTOj+etWl1IKZjDV0/2nsq+LmAkDv1MNM4DFftztf8emzHxNJ1gWoX87UpyHZ w4VzcuR7oQc2lnYFEIJPXVfJ656oeaDq78r0dcLuJqRGhZxN7B8gi9CMFuyOygfZA9vn zuyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4maoe/6kjxLiaB9SmdalwoLBVBEkYyNyCd2Sc9hJbV0=; b=WbSh+QQ/pYufYruYeoR/vQpjsZRcMe+L2LKPg3OiZAG+gr6OYCz4nZpwrY2TmCCnCo 7Tk62uvicytHL7gvQONSPCDkn/CEyR1Wv7dB5f+UYXAMja4WE2qgXHsGDyjFREgxhwDl a4p/nhY0IjN159fE/qgI1fJx4k4Mg2iT1+wdSRuxMZWRWl619sw/mb8knX3W5RlssFo5 yo4NGakz07niNIU3Lg1ckykn7UzhkwFsR8O2pEAbgJSzPaNiZD9Pig/gGO+cZOAunY/q UVoMRcK63vwRISGjftCB+sLy9nC5G+lpOlae/gGgTfLfRAYXLpKMn2opPIZu425L+DU0 msRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=JJDzqrDn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sg10-20020a170907a40a00b0078d00203ab2si4924489ejc.41.2022.10.28.06.06.42; Fri, 28 Oct 2022 06:07:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=JJDzqrDn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230164AbiJ1NFe (ORCPT + 99 others); Fri, 28 Oct 2022 09:05:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230312AbiJ1NFB (ORCPT ); Fri, 28 Oct 2022 09:05:01 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D560030559; Fri, 28 Oct 2022 06:04:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666962296; x=1698498296; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rVdNzdBQO+N6n0DeTiUUzVhpCEMcLGmACZM8CQ8W5rc=; b=JJDzqrDntEehz1g+TxJTR/flw4dwvW0jRy2sdFiPkr7jikgddJnAZTOd AoGJlDO1+ZNu7cyWrh+Y2C8BSVbq7pZd7eeg2thfLBf3/NEFiKAQoFgyy ZYFvqQ8WXEI1xQF/z3JmUDVPhpAlaljWFWXMVyabwtMrDhoXNxKvH7ymZ dU0rn1zMRoEDPFwY78h3l8oRtDyi5MA8DRQqjNsku7h7s8+oD74rZwOEW zsrXobBsM0CrqxvtUOilQGswcnIoZytCLA6foNmrKsoTDp+iCFXjvkrcV WNOjM+FYAwd6IuQw7U46bKS7Yxe0nEnSd9NFq4ofpjYgZCcyn5ewn6doA g==; X-IronPort-AV: E=Sophos;i="5.95,221,1661842800"; d="scan'208";a="120801638" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Oct 2022 06:04:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 28 Oct 2022 06:04:54 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 28 Oct 2022 06:04:50 -0700 From: Daniel Machon To: CC: , , , , , , , , , , , , , , , , , Subject: [PATCH net-next v5 6/6] net: microchip: sparx5: add support for offloading default prio Date: Fri, 28 Oct 2022 15:14:03 +0200 Message-ID: <20221028131403.1055694-7-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221028131403.1055694-1-daniel.machon@microchip.com> References: <20221028131403.1055694-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747936797503766369?= X-GMAIL-MSGID: =?utf-8?q?1747936797503766369?= Add support for offloading default prio {ETHERTYPE, 0, prio}. Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_dcb.c | 12 ++++++++++ .../ethernet/microchip/sparx5/sparx5_port.c | 23 +++++++++++++++++++ .../ethernet/microchip/sparx5/sparx5_port.h | 5 ++++ 3 files changed, 40 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c index 283d5f338e0e..df2374e64b72 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c @@ -34,6 +34,13 @@ static int sparx5_dcb_app_validate(struct net_device *dev, int err = 0; switch (app->selector) { + /* Default priority checks */ + case IEEE_8021QAZ_APP_SEL_ETHERTYPE: + if (app->protocol != 0) + err = -EINVAL; + else if (app->priority >= SPX5_PRIOS) + err = -ERANGE; + break; /* Dscp checks */ case IEEE_8021QAZ_APP_SEL_DSCP: if (app->protocol > 63) @@ -122,6 +129,11 @@ static int sparx5_dcb_app_update(struct net_device *dev) dscp_map = &qos.dscp.map; pcp_map = &qos.pcp.map; + /* Get default prio. */ + qos.default_prio = dcb_ieee_getapp_default_prio_mask(dev); + if (qos.default_prio) + qos.default_prio = fls(qos.default_prio) - 1; + /* Get dscp ingress mapping */ for (i = 0; i < ARRAY_SIZE(dscp_map->map); i++) { app_itr.selector = IEEE_8021QAZ_APP_SEL_DSCP; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index fb5e321c4896..73ebe76d7e50 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1151,6 +1151,7 @@ int sparx5_port_qos_set(struct sparx5_port *port, { sparx5_port_qos_dscp_set(port, &qos->dscp); sparx5_port_qos_pcp_set(port, &qos->pcp); + sparx5_port_qos_default_set(port, qos); return 0; } @@ -1220,3 +1221,25 @@ int sparx5_port_qos_dscp_set(const struct sparx5_port *port, return 0; } + +int sparx5_port_qos_default_set(const struct sparx5_port *port, + const struct sparx5_port_qos *qos) +{ + struct sparx5 *sparx5 = port->sparx5; + + /* Set default prio and dp level */ + spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) | + ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(0), + ANA_CL_QOS_CFG_DEFAULT_QOS_VAL | + ANA_CL_QOS_CFG_DEFAULT_DP_VAL, + sparx5, ANA_CL_QOS_CFG(port->portno)); + + /* Set default pcp and dei for untagged frames */ + spx5_rmw(ANA_CL_VLAN_CTRL_PORT_PCP_SET(0) | + ANA_CL_VLAN_CTRL_PORT_DEI_SET(0), + ANA_CL_VLAN_CTRL_PORT_PCP | + ANA_CL_VLAN_CTRL_PORT_DEI, + sparx5, ANA_CL_VLAN_CTRL(port->portno)); + + return 0; +} diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h index a0cd53fa3ad0..588eecff59f8 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h @@ -114,6 +114,7 @@ struct sparx5_port_qos_dscp { struct sparx5_port_qos { struct sparx5_port_qos_pcp pcp; struct sparx5_port_qos_dscp dscp; + u8 default_prio; }; int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos); @@ -123,4 +124,8 @@ int sparx5_port_qos_pcp_set(const struct sparx5_port *port, int sparx5_port_qos_dscp_set(const struct sparx5_port *port, struct sparx5_port_qos_dscp *qos); + +int sparx5_port_qos_default_set(const struct sparx5_port *port, + const struct sparx5_port_qos *qos); + #endif /* __SPARX5_PORT_H__ */