From patchwork Fri Oct 28 09:43:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12194 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp727188wru; Fri, 28 Oct 2022 02:50:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6wiYKy1+EX4ZWL28nNrrvJ4/bxFbQoDELdh49KKVi3DS9bhpBttl0C6bf1Ehn/cCmf2fBX X-Received: by 2002:aa7:d91a:0:b0:462:d2f6:26c6 with SMTP id a26-20020aa7d91a000000b00462d2f626c6mr1824930edr.180.1666950622216; Fri, 28 Oct 2022 02:50:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666950622; cv=none; d=google.com; s=arc-20160816; b=o9/Tri73a0x5x/LOt7l8h8YJpEEHlwnbQOOviH+6FPr5AGSlVOVzyBqr4MBMcofaCx +E/2kkCzX7cmnNbq7PuHsBNNY6UsnMqK/CkpBGL6WR8ytXWsS8kalmdAQI320CDZ/Tw7 yr1iFgwi+gp2ZzEfUsWIkW7cHJ5+Kw4YjAJJRhLw27pjmaVmN1jSSRgtSViGoUAUXFzZ l6Vha/EJn4Ed+75VKFh2CZ6XUkb8ENJLNtWRjTrdB1GOUXTSEofV8LtuVRGm76gXh3Zg 5xBBYB/PaBVxSlLatB7iPcAkO7Uy4dZY5e/Tx92kP4FzPIVfGMJUCfqCjhbWDChpz5DQ /Uyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=VBfEs4tVvu1FX5R5hBpYfxbDL/kM262uozbK/j71Z48=; b=wdzBZILSBPQs3SyubbTLbX9Lw3433WKw6MqbsIT0XFKhB9mTVBPrCxBxFclU5WW5GQ ggiXedG6mCn0AgkBJIZEjt3vLivMVbx0cqxOXyPj8VUumsOK9Jyk3oyGM1mQuLX3DjW1 eKehAMVxdUzm6MRYNzTd5ozR1rwgrEX3KGr1Y0GSZmw9BsOZXTjVaU+zR0aXuiMT0WCt L3LjQX/zQ1L1k7MqZPwnjA7yzibdA90ScPTZ8hqBWstVBezTvAAov1POVAQWxMtAuW88 r5mRLNiPLu8MOv40dig2dVHweaxl3kvVRgV0KmO6Q4gr4xtMqg/22zX/Khzf++hJ1DXq sp5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Yj0MOlR7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h4-20020a056402280400b0045440929f87si1184429ede.86.2022.10.28.02.49.54; Fri, 28 Oct 2022 02:50:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Yj0MOlR7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229927AbiJ1Jni (ORCPT + 99 others); Fri, 28 Oct 2022 05:43:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229691AbiJ1Jna (ORCPT ); Fri, 28 Oct 2022 05:43:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B219D1911FA; Fri, 28 Oct 2022 02:43:29 -0700 (PDT) X-UUID: c74a935848be4576b982fcd3366d7d0d-20221028 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VBfEs4tVvu1FX5R5hBpYfxbDL/kM262uozbK/j71Z48=; b=Yj0MOlR7Br3oUOwQ2mrvN5LT0AFplbI2MQBJjrpMz9zXJfO9GtMkEnmZ/XO4MHXPmTff/fDsuOqWTQVYfh9RyVBTsLBX/W/ZqtaIQPSGi6R/lPTDTLfxwZ5GhUtgmrivGwvt0haMZG4C7cSrCvZPXcLhnd5EMFpUFxa3ujBch2c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:58a2435f-ca74-476e-babe-1a6170129bbb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.12,REQID:58a2435f-ca74-476e-babe-1a6170129bbb,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:62cd327,CLOUDID:3da5bfea-84ac-4628-a416-bc50d5503da6,B ulkID:221028174327F2KFD9HJ,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c74a935848be4576b982fcd3366d7d0d-20221028 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2090798610; Fri, 28 Oct 2022 17:43:26 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 28 Oct 2022 17:43:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 28 Oct 2022 17:43:22 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Tinghan Shen , Irui Wang Subject: [PATCH v4 3/3] arm64: dts: mt8195: Add venc node Date: Fri, 28 Oct 2022 17:43:17 +0800 Message-ID: <20221028094317.29270-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221028094317.29270-1-tinghan.shen@mediatek.com> References: <20221028094317.29270-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747924415813387226?= X-GMAIL-MSGID: =?utf-8?q?1747924415813387226?= Add venc node for mt8195 SoC. Signed-off-by: Irui Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 97de03267884..2a29ec3bfdd7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2109,6 +2109,30 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: video-codec@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = ; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>;