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From: Bjorn Andersson <quic_bjorande@quicinc.com>
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Subject: [PATCH 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node
Date: Thu, 27 Oct 2022 20:41:52 -0700
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|
| Series |
interconnect: osm-l3: SC8280XP L3 and DDR scaling
|
|
Commit Message
Bjorn Andersson
Oct. 28, 2022, 3:41 a.m. UTC
Add a device node for the EPSS L3 frequency domain.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ed806a6e20f6..ba404a31206e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1791,6 +1791,16 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; + reg = <0 0x18590000 0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>,