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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t8-20020a170902e84800b001846e0e0511si2923630plg.226.2022.10.27.11.18.29; Thu, 27 Oct 2022 11:18:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="nz3/vOOL"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236337AbiJ0SOH (ORCPT + 99 others); Thu, 27 Oct 2022 14:14:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236266AbiJ0SOA (ORCPT ); Thu, 27 Oct 2022 14:14:00 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47338193DF; Thu, 27 Oct 2022 11:13:59 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29RIDe53037314; Thu, 27 Oct 2022 13:13:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666894420; bh=M19qasxhP6nigW+ai02utN8S5S0aOUYmDLwWllKur00=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nz3/vOOLTAAgFhPU1GfMmviLMaWYog9MO53bkXVjd44yJqdwRJDHZ9Xcq5ym1Y/Dq IcMHR3AA8HMDtgnISdIgp9/8eQrWfxwMWqT21SWLRuNj10RuapQTQ8K6yg3JrhqvN1 nAKpkein5T8odgEpAcu0FzDHSi0Hwsf4iLKI4qAA= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29RIDefr065688 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Oct 2022 13:13:40 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Thu, 27 Oct 2022 13:13:40 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Thu, 27 Oct 2022 13:13:40 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29RIDbdx108447; Thu, 27 Oct 2022 13:13:39 -0500 From: Andrew Davis To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt CC: , , , Andrew Davis Subject: [PATCH v3 3/9] ARM: dts: nspire: Fix cpu node to conform with DT binding Date: Thu, 27 Oct 2022 13:13:31 -0500 Message-ID: <20221027181337.8651-4-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221027181337.8651-1-afd@ti.com> References: <20221027181337.8651-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747865799829607351?= X-GMAIL-MSGID: =?utf-8?q?1747865799829607351?= This node does not follow the DT binding schema, correct this. Should result in no functional change. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/nspire.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index 48fbc9d533c3..cb7237051512 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -11,8 +11,13 @@ / { interrupt-parent = <&intc>; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; }; };