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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id p22-20020aa7d316000000b00461c1804cdasm942868edq.3.2022.10.27.05.34.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 05:34:57 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v1 3/5] dt-bindings: clock: dispcc-sm8250: Add EDP_LINK_DIV_CLK_SRC index Date: Thu, 27 Oct 2022 14:34:30 +0200 Message-Id: <20221027123432.1818530-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027123432.1818530-1-robert.foss@linaro.org> References: <20221027123432.1818530-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747844734084378734?= X-GMAIL-MSGID: =?utf-8?q?1747844734084378734?= Add this previously missing index, since it is supported by the SoCs targeted by the dispcc-sm8250 driver. Signed-off-by: Robert Foss Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,dispcc-sm8250.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h index ce001cbbc27f..767fdb27e514 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm8250.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h @@ -64,6 +64,7 @@ #define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 #define DISP_CC_MDSS_EDP_PIXEL_CLK 55 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 +#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 57 /* DISP_CC Reset */ #define DISP_CC_MDSS_CORE_BCR 0