| Message ID | 20221027074652.1044235-4-dmitry.torokhov@gmail.com |
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From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Mark Brown <broonie@kernel.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Banajit Goswami <bgoswami@quicinc.com>,
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linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 4/6] arm64: dts: qcom: sc7280: fix codec reset line polarity
for CRD 3.0/3.1
Date: Thu, 27 Oct 2022 00:46:50 -0700
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| Series |
[1/6] arm64: dts: qcom: msm8996: fix sound card reset line polarity
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Commit Message
Dmitry Torokhov
Oct. 27, 2022, 7:46 a.m. UTC
The driver for the codec, when resetting the chip, first drives the line
low, and then high. This means that the line is active low. Change the
annotation in the DTS accordingly.
Fixes: 0a3a56a93fd9 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 3.0/3.1")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
---
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index a42b5878a75f..df49564ae6dc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -37,7 +37,7 @@ wcd9385: audio-codec-1 { pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>; - reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; qcom,rx-device = <&wcd_rx>;