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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e15-20020a656bcf000000b0043966935b33si7230455pgw.166.2022.10.26.12.08.12; Wed, 26 Oct 2022 12:08:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=UuoAHjyj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234865AbiJZTH6 (ORCPT + 99 others); Wed, 26 Oct 2022 15:07:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234016AbiJZTHc (ORCPT ); Wed, 26 Oct 2022 15:07:32 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B28362FFF9; Wed, 26 Oct 2022 12:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1666811102; x=1698347102; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JdzvmHcIkvcvVmbWai2BfnkIiIjIZv5mmWfuR6jezCY=; b=UuoAHjyjwjamvlYX1LKjaIQxL9kMA+BpaxYec+Gf00V6FlLlSIZIPTol cXwwJWa7EIHYWVCVsz8ahNxMK/sqAuKiv28nC4+GZltImi2vcLPSZzhMU rMBZo1gHQHadVKiJxNQmbuQpbuGARHLHyS7k5BkY+Oy3KphfYkhlue9Zx k=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 26 Oct 2022 12:04:55 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2022 12:04:55 -0700 Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 12:04:54 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , Marc Zyngier CC: Taniya Das , , , , , Melody Olvera Subject: [PATCH v3 4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks Date: Wed, 26 Oct 2022 12:04:40 -0700 Message-ID: <20221026190441.4002212-5-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026190441.4002212-1-quic_molvera@quicinc.com> References: <20221026190441.4002212-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747778331812960879?= X-GMAIL-MSGID: =?utf-8?q?1747778331812960879?= Add support for RMPh clocks for QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- drivers/clk/qcom/clk-rpmh.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 0471bab82464..1da45a6e2f29 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -644,6 +644,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = { .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), }; +DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); + +static struct clk_hw *qdu1000_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { + .clks = qdu1000_rpmh_clocks, + .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -727,6 +739,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) } static const struct of_device_id clk_rpmh_match_table[] = { + { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},