From patchwork Wed Oct 26 14:16:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp295448wru; Wed, 26 Oct 2022 07:19:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5rqK8EGdXtpbDlyLcYaLln/vRm5B0whXM5jM2+qlTrAJ2xgmLj+zUV226fuyOTAtfzduYN X-Received: by 2002:a17:902:db0b:b0:185:51cc:8113 with SMTP id m11-20020a170902db0b00b0018551cc8113mr42757753plx.64.1666793939220; Wed, 26 Oct 2022 07:18:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666793939; cv=none; d=google.com; s=arc-20160816; b=pTSrnz/4JVtvIJwd8O5s/u6B4qYq3Nw7UIXIUf8mzQxEiOTjGBdMpJ9dk4YBYA7J8v pxYxYGc9wHkQQaJ1R1x1011DKYaYhAEoV8F01U61KZThLMXHRzOBcqjVh/Tyu8AgxQQb OcoC6jJ6n/9ATnS1pcQQCM7BiLfMUAmH/rQg2Bp71dzZI5sexH0t97+oSvEZRV46gZ+5 fZpEg1tph+bPeOuQp/Pi9LWqq65CnpoXU7BZXRkF0nRSEAKyEbpSp9F5p+B2TSLVBlyH sNRaozxZpzYIcWGZ6YI84/j8gnvpEmJ23E/1MOnIQBJFza9KrPadQrFjNpBAtjUxpl0C ei0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UlMEe9j8VJQYeR2TObf5Xg7bXZtNnQaKJ+q2NCjzZMY=; b=Z7/vyYAH2/c47AQlAJdOv8nSNe1i3FwLcIQkG0Q6AU7PXqxy8KjCQ04yCgV8sV2S+N BkU/8h1fjgqHIRFOaxeF5PdPjp52gp9rgNOBh7otxapd30CFGsU3yzKmu8YnUCpIsgQf 1lnK/+t5Q03IyD8cSBnzS1mWhCDDLsKW7z/F5Vlq0MH6/L9SdQq181o1zkyryPTPeMtR E8fmhhW94Qzo1uGJlsq+9fThmV7aBZGhCMd91lapbh79Va4AEbUUa+II2G/ahg611VFA PmtmwYMhe2Hx53sxRNmsLG4fyzPmkY7W5netbRtxpVqWtLY41fzIp+4cg+68q2zwia8o yxrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iniyl5UY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t4-20020a656084000000b0045a048683dcsi5987447pgu.236.2022.10.26.07.18.45; Wed, 26 Oct 2022 07:18:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iniyl5UY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234217AbiJZOQz (ORCPT + 99 others); Wed, 26 Oct 2022 10:16:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234221AbiJZOQu (ORCPT ); Wed, 26 Oct 2022 10:16:50 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A85610F881; Wed, 26 Oct 2022 07:16:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2BA78B822B3; Wed, 26 Oct 2022 14:16:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94B68C43143; Wed, 26 Oct 2022 14:16:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666793806; bh=20zEspJzMm9fflHXzbJ8RnT9WirOG5GHjev3+HrUS8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iniyl5UY1LvOsCYnn2hXyaYBmj0zNdLE7/xJmDtUT12Gsa+C9ki81nB0bewpGT5zv n1jFBUj+LYHhoTgX04OZ/g1qvWqlY9T1ZIXsl377gAnTvd5Ul6iO8fUHWdQdhkjHTK pdpyKLk2219g+G3/Z40KUTeBTZWJLxDMX29Muo0vY3NnsYei+cbj/y9OaUG8lpenBY euZnNK+bXJK9hd/NuFQGkmfez6b8b74gGBKgblZvjc++FnD5bb/8EPXXCs+bjaJnSX UlfHtTgOoTY7atAQMmIF5xc6iRxAP4x0UDlAqCEuyPhHer4z8MsXGSLqjtQIYh+K4e 6lDj8qrrLuwwQ== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv6 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Date: Wed, 26 Oct 2022 09:16:29 -0500 Message-Id: <20221026141631.696863-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org> References: <20221026141631.696863-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747760121800963189?= X-GMAIL-MSGID: =?utf-8?q?1747760121800963189?= The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen --- v6: not getting the clk-phase-sd-hs is not a hard failure v5: change error handling from of_property_read_variable_u32_array() support arm32 by reading the reg_shift v4: no change v3: add space before &socfpga_drv_data v2: simplify clk-phase calculations make property optional in driver --- drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..fff6222d58e4 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include #include #include +#include +#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ + ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,44 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset, reg_shift; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc < 0) { + dev_info(host->dev, "Optional: clk-phase-sd-hs not found!\n"); + return 0; + } + + sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + dev_info(host->dev, "Optional: failed to find altr,sys-mgr regmap!\n"); + return 0; + } + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, };